/* EADC clock source is HCLK(72MHz), set divider to 8, ADC clock is 72/8 MHz */
CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
// /* Configure the GPB9 for ADC analog input pins. */
// SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk);
// SYS->GPB_MFPH |= SYS_GPB_MFPH_PB9MFP_EADC_CH6 | SYS_GPB_MFPH_PB10MFP_EADC_CH7;
// /* Disable the GPB9 digital input path to avoid the leakage current. */
// GPIO_DISABLE_DIGITAL_PATH(PB, BIT9);
// GPIO_DISABLE_DIGITAL_PATH(PB, BIT10);
/* Set the ADC internal sampling time, input mode as single-end and enable the A/D converter */
EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END);
EADC_SetInternalSampleTime(EADC, 6);
/* Configure the sample module 0 for analog input channel 6 and software trigger source.*/
// EADC_ConfigSampleModule(EADC, 16, EADC_SOFTWARE_TRIGGER, 16);
// EADC_ConfigSampleModule(EADC, 17, EADC_SOFTWARE_TRIGGER, 17);