; generated by Component: ARM Compiler 5.05 (build 41) Tool: ArmCC [4d0eb9]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\spi.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\spi.d --cpu=Cortex-M0 --apcs=interwork -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\Mini51Series\Include -I..\..\..\Library\StdDriver\inc -I.\StdDriver\inc -I.\CMSIS -IG:\Geek\Projects\Zulolo_F\Force\Code\Zulolo_F_Force\RTE -ID:\Keil_v5\ARM\PACK\Nuvoton\NuMicro_DFP\1.0.2\Device\Mini51\Include -ID:\Keil_v5\ARM\CMSIS\Include -I\ -D__MICROLIB --omf_browse=.\obj\spi.crf StdDriver\src\spi.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  SPI_Open PROC
;;;37       */
;;;38     uint32_t SPI_Open(SPI_T *spi,
000000  b5f8              PUSH     {r3-r7,lr}
;;;39                        uint32_t u32MasterSlave, 
;;;40                        uint32_t u32SPIMode,  
;;;41                        uint32_t u32DataWidth,
;;;42                        uint32_t u32BusClock)
;;;43     {
000002  4604              MOV      r4,r0
;;;44         uint32_t u32Pclk, u32Div;
;;;45         
;;;46         // assert if is as slave but busclock isn't equal 0
;;;47         //
;;;48         
;;;49         /* Enable SPI clock */
;;;50         CLK->APBCLK |= CLK_APBCLK_SPI_EN_Msk;
000004  487b              LDR      r0,|L1.500|
000006  9f06              LDR      r7,[sp,#0x18]
000008  6885              LDR      r5,[r0,#8]
00000a  2601              MOVS     r6,#1
00000c  0336              LSLS     r6,r6,#12
00000e  4335              ORRS     r5,r5,r6
000010  6085              STR      r5,[r0,#8]
;;;51             
;;;52         if(u32DataWidth == 32)
000012  2b20              CMP      r3,#0x20
000014  d100              BNE      |L1.24|
;;;53             u32DataWidth = 0;
000016  2300              MOVS     r3,#0
                  |L1.24|
;;;54             
;;;55         spi->CNTRL = u32MasterSlave | (u32DataWidth << SPI_CNTRL_TX_BIT_LEN_Pos) | (u32SPIMode);
000018  00d8              LSLS     r0,r3,#3
00001a  4308              ORRS     r0,r0,r1
00001c  4310              ORRS     r0,r0,r2
00001e  6020              STR      r0,[r4,#0]
;;;56         
;;;57         u32Pclk = CLK_GetHCLKFreq();
000020  f7fffffe          BL       CLK_GetHCLKFreq
;;;58         
;;;59         u32Div = 0xffff; 
000024  4d74              LDR      r5,|L1.504|
000026  4606              MOV      r6,r0                 ;57
000028  4628              MOV      r0,r5
;;;60             
;;;61         if(u32BusClock !=0 )
00002a  2f00              CMP      r7,#0
00002c  d015              BEQ      |L1.90|
;;;62         {
;;;63             u32Div = (((u32Pclk / u32BusClock) + 1) >> 1) - 1;
00002e  4639              MOV      r1,r7
000030  4630              MOV      r0,r6
000032  f7fffffe          BL       __aeabi_uidivmod
000036  1c40              ADDS     r0,r0,#1
000038  0840              LSRS     r0,r0,#1
00003a  1e40              SUBS     r0,r0,#1
;;;64             if(u32Div > 0xFFFF)
00003c  42a8              CMP      r0,r5
00003e  d900              BLS      |L1.66|
;;;65                 u32Div = 0xFFFF;
000040  4628              MOV      r0,r5
                  |L1.66|
;;;66             spi->DIVIDER = (SPI->DIVIDER & ~0xffff) | u32Div;
000042  496e              LDR      r1,|L1.508|
000044  6849              LDR      r1,[r1,#4]
000046  0c09              LSRS     r1,r1,#16
000048  0409              LSLS     r1,r1,#16
00004a  4301              ORRS     r1,r1,r0
                  |L1.76|
;;;67         }
;;;68         else
;;;69             spi->DIVIDER = 0;
00004c  6061              STR      r1,[r4,#4]
;;;70         
;;;71         return ( u32Pclk / ((u32Div+1)*2) );
00004e  0041              LSLS     r1,r0,#1
000050  4630              MOV      r0,r6
000052  1c89              ADDS     r1,r1,#2
000054  f7fffffe          BL       __aeabi_uidivmod
;;;72     }
000058  bdf8              POP      {r3-r7,pc}
                  |L1.90|
00005a  2100              MOVS     r1,#0                 ;69
00005c  e7f6              B        |L1.76|
;;;73     
                          ENDP

                  SPI_Close PROC
;;;78       */
;;;79     void SPI_Close(SPI_T *spi)
00005e  2005              MOVS     r0,#5
;;;80     {
;;;81         /* Rreset SPI */
;;;82         SYS->IPRSTC2 |= SYS_IPRSTC2_SPI_RST_Msk;
000060  0700              LSLS     r0,r0,#28
000062  68c2              LDR      r2,[r0,#0xc]
000064  2101              MOVS     r1,#1
000066  0309              LSLS     r1,r1,#12
000068  430a              ORRS     r2,r2,r1
00006a  60c2              STR      r2,[r0,#0xc]
;;;83         SYS->IPRSTC2 &= ~SYS_IPRSTC2_SPI_RST_Msk;
00006c  68c2              LDR      r2,[r0,#0xc]
00006e  438a              BICS     r2,r2,r1
000070  60c2              STR      r2,[r0,#0xc]
;;;84         
;;;85         /* Disable SPI clock */
;;;86         CLK->APBCLK &= ~CLK_APBCLK_SPI_EN_Msk;
000072  4860              LDR      r0,|L1.500|
000074  6882              LDR      r2,[r0,#8]
000076  438a              BICS     r2,r2,r1
000078  6082              STR      r2,[r0,#8]
;;;87     }
00007a  4770              BX       lr
;;;88     
                          ENDP

                  SPI_ClearRxFIFO PROC
;;;93       */
;;;94     void SPI_ClearRxFIFO(SPI_T *spi)
00007c  6c01              LDR      r1,[r0,#0x40]
;;;95     {
;;;96         spi->FIFO_CTL |= SPI_FIFO_CTL_RX_CLR_Msk;
00007e  2201              MOVS     r2,#1
000080  4311              ORRS     r1,r1,r2
000082  6401              STR      r1,[r0,#0x40]
;;;97     }
000084  4770              BX       lr
;;;98     
                          ENDP

                  SPI_ClearTxFIFO PROC
;;;103      */
;;;104    void SPI_ClearTxFIFO(SPI_T *spi)
000086  6c01              LDR      r1,[r0,#0x40]
;;;105    {
;;;106        spi->FIFO_CTL |= SPI_FIFO_CTL_TX_CLR_Msk;
000088  2202              MOVS     r2,#2
00008a  4311              ORRS     r1,r1,r2
00008c  6401              STR      r1,[r0,#0x40]
;;;107    }
00008e  4770              BX       lr
;;;108    
                          ENDP

                  SPI_DisableAutoSS PROC
;;;113      */
;;;114    void SPI_DisableAutoSS(SPI_T *spi)
000090  6881              LDR      r1,[r0,#8]
;;;115    {
;;;116        spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
000092  2208              MOVS     r2,#8
000094  4391              BICS     r1,r1,r2
000096  6081              STR      r1,[r0,#8]
;;;117    }
000098  4770              BX       lr
;;;118    
                          ENDP

                  SPI_EnableAutoSS PROC
;;;125      */
;;;126    void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
00009a  6883              LDR      r3,[r0,#8]
;;;127    {
;;;128        spi->SSR |= (u32SSPinMask | u32ActiveLevel) | SPI_SSR_AUTOSS_Msk;
00009c  430b              ORRS     r3,r3,r1
00009e  2108              MOVS     r1,#8
0000a0  430a              ORRS     r2,r2,r1
0000a2  4313              ORRS     r3,r3,r2
0000a4  6083              STR      r3,[r0,#8]
;;;129    }
0000a6  4770              BX       lr
;;;130    
                          ENDP

                  SPI_SetBusClock PROC
;;;136      */
;;;137    uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
0000a8  b5f8              PUSH     {r3-r7,lr}
;;;138    {
0000aa  460f              MOV      r7,r1
0000ac  4604              MOV      r4,r0
;;;139        uint32_t u32Pclk = CLK_GetHCLKFreq();
0000ae  f7fffffe          BL       CLK_GetHCLKFreq
;;;140        uint32_t u32Div = 0xffff; 
0000b2  4d51              LDR      r5,|L1.504|
0000b4  4606              MOV      r6,r0                 ;139
0000b6  4628              MOV      r0,r5
;;;141            
;;;142        if(u32BusClock !=0 )
0000b8  2f00              CMP      r7,#0
0000ba  d015              BEQ      |L1.232|
;;;143        {
;;;144            u32Div = (((u32Pclk / u32BusClock) + 1) >> 1) - 1;
0000bc  4639              MOV      r1,r7
0000be  4630              MOV      r0,r6
0000c0  f7fffffe          BL       __aeabi_uidivmod
0000c4  1c40              ADDS     r0,r0,#1
0000c6  0840              LSRS     r0,r0,#1
0000c8  1e40              SUBS     r0,r0,#1
;;;145            if(u32Div > 0xFFFF)
0000ca  42a8              CMP      r0,r5
0000cc  d900              BLS      |L1.208|
;;;146                u32Div = 0xFFFF;
0000ce  4628              MOV      r0,r5
                  |L1.208|
;;;147            spi->DIVIDER = (SPI->DIVIDER & ~0xffff) | u32Div;
0000d0  494a              LDR      r1,|L1.508|
0000d2  6849              LDR      r1,[r1,#4]
0000d4  0c09              LSRS     r1,r1,#16
0000d6  0409              LSLS     r1,r1,#16
0000d8  4301              ORRS     r1,r1,r0
                  |L1.218|
;;;148        }
;;;149        else
;;;150            spi->DIVIDER = 0;
0000da  6061              STR      r1,[r4,#4]
;;;151        
;;;152        return ( u32Pclk / ((u32Div+1)*2) );
0000dc  0041              LSLS     r1,r0,#1
0000de  4630              MOV      r0,r6
0000e0  1c89              ADDS     r1,r1,#2
0000e2  f7fffffe          BL       __aeabi_uidivmod
;;;153    }
0000e6  bdf8              POP      {r3-r7,pc}
                  |L1.232|
0000e8  2100              MOVS     r1,#0                 ;150
0000ea  e7f6              B        |L1.218|
;;;154    
                          ENDP

                  SPI_EnableFIFO PROC
;;;161      */
;;;162    void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
0000ec  b510              PUSH     {r4,lr}
;;;163    {
;;;164        spi->FIFO_CTL = (spi->FIFO_CTL & ~(SPI_FIFO_CTL_TX_THRESHOLD_Msk | SPI_FIFO_CTL_RX_THRESHOLD_Msk) | 
0000ee  6c03              LDR      r3,[r0,#0x40]
0000f0  2433              MOVS     r4,#0x33
0000f2  0624              LSLS     r4,r4,#24
0000f4  43a3              BICS     r3,r3,r4
0000f6  0709              LSLS     r1,r1,#28
0000f8  430b              ORRS     r3,r3,r1
0000fa  0611              LSLS     r1,r2,#24
0000fc  430b              ORRS     r3,r3,r1
0000fe  6403              STR      r3,[r0,#0x40]
;;;165                                (u32TxThreshold << SPI_FIFO_CTL_TX_THRESHOLD_Pos) |
;;;166                                (u32RxThreshold << SPI_FIFO_CTL_RX_THRESHOLD_Pos));
;;;167        
;;;168        spi->CNTRL |= SPI_CNTRL_FIFO_Msk;
000100  6801              LDR      r1,[r0,#0]
000102  2201              MOVS     r2,#1
000104  0552              LSLS     r2,r2,#21
000106  4311              ORRS     r1,r1,r2
000108  6001              STR      r1,[r0,#0]
;;;169    }
00010a  bd10              POP      {r4,pc}
;;;170    
                          ENDP

                  SPI_DisableFIFO PROC
;;;175      */  
;;;176    void SPI_DisableFIFO(SPI_T *spi)
00010c  6801              LDR      r1,[r0,#0]
;;;177    {
;;;178        spi->CNTRL &= ~SPI_CNTRL_FIFO_Msk;
00010e  2201              MOVS     r2,#1
000110  0552              LSLS     r2,r2,#21
000112  4391              BICS     r1,r1,r2
000114  6001              STR      r1,[r0,#0]
;;;179    }
000116  4770              BX       lr
;;;180    
                          ENDP

                  SPI_GetBusClock PROC
;;;185      */ 
;;;186    uint32_t SPI_GetBusClock(SPI_T *spi)
000118  b510              PUSH     {r4,lr}
;;;187    {
00011a  4604              MOV      r4,r0
;;;188        uint32_t u32Div;
;;;189        uint32_t u32ApbClock;
;;;190    
;;;191        u32ApbClock = CLK_GetHCLKFreq();
00011c  f7fffffe          BL       CLK_GetHCLKFreq
;;;192        u32Div = spi->DIVIDER & 0xff;
000120  6861              LDR      r1,[r4,#4]
;;;193        return ((u32ApbClock >> 1) / (u32Div + 1));                                                 
000122  0840              LSRS     r0,r0,#1
000124  b2c9              UXTB     r1,r1                 ;192
000126  1c49              ADDS     r1,r1,#1
000128  f7fffffe          BL       __aeabi_uidivmod
;;;194    }
00012c  bd10              POP      {r4,pc}
;;;195    
                          ENDP

                  SPI_EnableInt PROC
;;;205      */ 
;;;206    void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
00012e  07ca              LSLS     r2,r1,#31
;;;207    {
000130  d004              BEQ      |L1.316|
;;;208        if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
;;;209            spi->CNTRL |= SPI_CNTRL_IE_Msk;
000132  6802              LDR      r2,[r0,#0]
000134  2301              MOVS     r3,#1
000136  045b              LSLS     r3,r3,#17
000138  431a              ORRS     r2,r2,r3
00013a  6002              STR      r2,[r0,#0]
                  |L1.316|
;;;210        
;;;211        if((u32Mask & SPI_SS_INT_OPT_MASK) == SPI_SS_INT_OPT_MASK)
00013c  078a              LSLS     r2,r1,#30
00013e  d504              BPL      |L1.330|
;;;212            spi->CNTRL2 |= SPI_CNTRL2_SS_INT_OPT_Msk;
000140  6bc2              LDR      r2,[r0,#0x3c]
000142  2301              MOVS     r3,#1
000144  041b              LSLS     r3,r3,#16
000146  431a              ORRS     r2,r2,r3
000148  63c2              STR      r2,[r0,#0x3c]
                  |L1.330|
;;;213            
;;;214        if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
00014a  074a              LSLS     r2,r1,#29
00014c  d504              BPL      |L1.344|
;;;215            spi->CNTRL2 |= SPI_CNTRL2_SSTA_INTEN_Msk;
00014e  6bc2              LDR      r2,[r0,#0x3c]
000150  2301              MOVS     r3,#1
000152  029b              LSLS     r3,r3,#10
000154  431a              ORRS     r2,r2,r3
000156  63c2              STR      r2,[r0,#0x3c]
                  |L1.344|
;;;216        
;;;217        if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
000158  070a              LSLS     r2,r1,#28
00015a  d503              BPL      |L1.356|
;;;218            spi->FIFO_CTL |= SPI_FIFO_CTL_TX_INTEN_Msk;
00015c  6c02              LDR      r2,[r0,#0x40]
00015e  2308              MOVS     r3,#8
000160  431a              ORRS     r2,r2,r3
000162  6402              STR      r2,[r0,#0x40]
                  |L1.356|
;;;219        
;;;220        if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
000164  06ca              LSLS     r2,r1,#27
000166  d503              BPL      |L1.368|
;;;221            spi->FIFO_CTL |= SPI_FIFO_CTL_RX_INTEN_Msk;    
000168  6c02              LDR      r2,[r0,#0x40]
00016a  2304              MOVS     r3,#4
00016c  431a              ORRS     r2,r2,r3
00016e  6402              STR      r2,[r0,#0x40]
                  |L1.368|
;;;222        
;;;223        if((u32Mask & SPI_FIFO_RXOV_INTEN_MASK) == SPI_FIFO_RXOV_INTEN_MASK)
000170  2212              MOVS     r2,#0x12
000172  438a              BICS     r2,r2,r1
000174  d103              BNE      |L1.382|
;;;224            spi->FIFO_CTL |= SPI_FIFO_CTL_RXOV_INTEN_Msk;
000176  6c02              LDR      r2,[r0,#0x40]
000178  2340              MOVS     r3,#0x40
00017a  431a              ORRS     r2,r2,r3
00017c  6402              STR      r2,[r0,#0x40]
                  |L1.382|
;;;225        
;;;226        if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
00017e  2214              MOVS     r2,#0x14
000180  438a              BICS     r2,r2,r1
000182  d104              BNE      |L1.398|
;;;227            spi->FIFO_CTL |= SPI_FIFO_CTL_TIMEOUT_INTEN_Msk;        
000184  6c01              LDR      r1,[r0,#0x40]
000186  2201              MOVS     r2,#1
000188  0552              LSLS     r2,r2,#21
00018a  4311              ORRS     r1,r1,r2
00018c  6401              STR      r1,[r0,#0x40]
                  |L1.398|
;;;228    }
00018e  4770              BX       lr
;;;229    
                          ENDP

                  SPI_DisableInt PROC
;;;239      */ 
;;;240    void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
000190  07ca              LSLS     r2,r1,#31
;;;241    {
000192  d004              BEQ      |L1.414|
;;;242        if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
;;;243            spi->CNTRL &= ~SPI_CNTRL_IE_Msk;
000194  6802              LDR      r2,[r0,#0]
000196  2301              MOVS     r3,#1
000198  045b              LSLS     r3,r3,#17
00019a  439a              BICS     r2,r2,r3
00019c  6002              STR      r2,[r0,#0]
                  |L1.414|
;;;244        
;;;245        if((u32Mask & SPI_SS_INT_OPT_MASK) == SPI_SS_INT_OPT_MASK)
00019e  078a              LSLS     r2,r1,#30
0001a0  d504              BPL      |L1.428|
;;;246            spi->CNTRL2 &= ~SPI_CNTRL2_SS_INT_OPT_Msk;
0001a2  6bc2              LDR      r2,[r0,#0x3c]
0001a4  2301              MOVS     r3,#1
0001a6  041b              LSLS     r3,r3,#16
0001a8  439a              BICS     r2,r2,r3
0001aa  63c2              STR      r2,[r0,#0x3c]
                  |L1.428|
;;;247            
;;;248        if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
0001ac  074a              LSLS     r2,r1,#29
0001ae  d504              BPL      |L1.442|
;;;249            spi->CNTRL2 &= ~SPI_CNTRL2_SSTA_INTEN_Msk;
0001b0  6bc2              LDR      r2,[r0,#0x3c]
0001b2  2301              MOVS     r3,#1
0001b4  029b              LSLS     r3,r3,#10
0001b6  439a              BICS     r2,r2,r3
0001b8  63c2              STR      r2,[r0,#0x3c]
                  |L1.442|
;;;250        
;;;251        if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
0001ba  070a              LSLS     r2,r1,#28
0001bc  d503              BPL      |L1.454|
;;;252            spi->FIFO_CTL &= ~SPI_FIFO_CTL_TX_INTEN_Msk;
0001be  6c02              LDR      r2,[r0,#0x40]
0001c0  2308              MOVS     r3,#8
0001c2  439a              BICS     r2,r2,r3
0001c4  6402              STR      r2,[r0,#0x40]
                  |L1.454|
;;;253        
;;;254        if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
0001c6  06ca              LSLS     r2,r1,#27
0001c8  d503              BPL      |L1.466|
;;;255            spi->FIFO_CTL &= ~SPI_FIFO_CTL_RX_INTEN_Msk;
0001ca  6c02              LDR      r2,[r0,#0x40]
0001cc  2304              MOVS     r3,#4
0001ce  439a              BICS     r2,r2,r3
0001d0  6402              STR      r2,[r0,#0x40]
                  |L1.466|
;;;256        
;;;257        if((u32Mask & SPI_FIFO_RXOV_INTEN_MASK) == SPI_FIFO_RXOV_INTEN_MASK)
0001d2  2212              MOVS     r2,#0x12
0001d4  438a              BICS     r2,r2,r1
0001d6  d103              BNE      |L1.480|
;;;258            spi->FIFO_CTL &= ~SPI_FIFO_CTL_RXOV_INTEN_Msk;
0001d8  6c02              LDR      r2,[r0,#0x40]
0001da  2340              MOVS     r3,#0x40
0001dc  439a              BICS     r2,r2,r3
0001de  6402              STR      r2,[r0,#0x40]
                  |L1.480|
;;;259        
;;;260        if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
0001e0  2214              MOVS     r2,#0x14
0001e2  438a              BICS     r2,r2,r1
0001e4  d104              BNE      |L1.496|
;;;261            spi->FIFO_CTL &= ~SPI_FIFO_CTL_TIMEOUT_INTEN_Msk;        
0001e6  6c01              LDR      r1,[r0,#0x40]
0001e8  2201              MOVS     r2,#1
0001ea  0552              LSLS     r2,r2,#21
0001ec  4391              BICS     r1,r1,r2
0001ee  6401              STR      r1,[r0,#0x40]
                  |L1.496|
;;;262    }
0001f0  4770              BX       lr
;;;263    
                          ENDP

0001f2  0000              DCW      0x0000
                  |L1.500|
                          DCD      0x50000200
                  |L1.504|
                          DCD      0x0000ffff
                  |L1.508|
                          DCD      0x40030000

;*** Start embedded assembler ***

#line 1 "StdDriver\\src\\spi.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___5_spi_c_SPI_Open____REV16|
#line 118 ".\\CMSIS\\core_cmInstr.h"
|__asm___5_spi_c_SPI_Open____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___5_spi_c_SPI_Open____REVSH|
#line 132
|__asm___5_spi_c_SPI_Open____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
