; generated by Component: ARM Compiler 5.04 update 1 (build 49) Tool: ArmCC [5040049]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\clk.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\clk.d --cpu=Cortex-M0 --apcs=interwork -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\NM1120\Include -I..\..\..\..\Library\StdDriver\inc -I.\source -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\clk.crf ..\..\..\..\Library\StdDriver\src\clk.c]
                          THUMB

                          AREA ||i.CLK_DisableCKO||, CODE, READONLY, ALIGN=2

                  CLK_DisableCKO PROC
;;;32       */
;;;33     void CLK_DisableCKO(void)
000000  4802              LDR      r0,|L1.12|
;;;34     {
;;;35         /* Disable CKO clock source */
;;;36         CLK->CLKOCTL &= (~CLK_CLKOCTL_CLKOEN_Msk);
000002  6a01              LDR      r1,[r0,#0x20]
000004  2210              MOVS     r2,#0x10
000006  4391              BICS     r1,r1,r2
000008  6201              STR      r1,[r0,#0x20]
;;;37     }
00000a  4770              BX       lr
;;;38     
                          ENDP

                  |L1.12|
                          DCD      0x50000240

                          AREA ||i.CLK_DisableModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_DisableModuleClock PROC
;;;363      */
;;;364    void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
000000  0f81              LSRS     r1,r0,#30
;;;365    {
;;;366        *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4))  &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
000002  008a              LSLS     r2,r1,#2
000004  4904              LDR      r1,|L2.24|
000006  1851              ADDS     r1,r2,r1
000008  684a              LDR      r2,[r1,#4]
00000a  06c3              LSLS     r3,r0,#27
00000c  0edb              LSRS     r3,r3,#27
00000e  2001              MOVS     r0,#1
000010  4098              LSLS     r0,r0,r3
000012  4382              BICS     r2,r2,r0
000014  604a              STR      r2,[r1,#4]
;;;367    }
000016  4770              BX       lr
;;;368    
                          ENDP

                  |L2.24|
                          DCD      0x50000200

                          AREA ||i.CLK_DisableSysTick||, CODE, READONLY, ALIGN=2

                  CLK_DisableSysTick PROC
;;;428      */
;;;429    void CLK_DisableSysTick(void)
000000  4901              LDR      r1,|L3.8|
;;;430    {
;;;431        SysTick->CTRL = 0;      /* Set System Tick counter disabled */
000002  2000              MOVS     r0,#0
000004  6108              STR      r0,[r1,#0x10]
;;;432    }
000006  4770              BX       lr
;;;433    
                          ENDP

                  |L3.8|
                          DCD      0xe000e000

                          AREA ||i.CLK_DisableXtalRC||, CODE, READONLY, ALIGN=2

                  CLK_DisableXtalRC PROC
;;;315      */
;;;316    void CLK_DisableXtalRC(uint32_t u32ClkMask)
000000  4902              LDR      r1,|L4.12|
;;;317    {
;;;318        CLK->PWRCTL &= ~u32ClkMask;
000002  680a              LDR      r2,[r1,#0]
000004  4382              BICS     r2,r2,r0
000006  600a              STR      r2,[r1,#0]
;;;319    }
000008  4770              BX       lr
;;;320    
                          ENDP

00000a  0000              DCW      0x0000
                  |L4.12|
                          DCD      0x50000200

                          AREA ||i.CLK_EnableCKO||, CODE, READONLY, ALIGN=2

                  CLK_EnableCKO PROC
;;;55       */
;;;56     void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
000000  b530              PUSH     {r4,r5,lr}
;;;57     {
000002  460d              MOV      r5,r1
000004  4614              MOV      r4,r2
;;;58         /* Select CKO clock source */
;;;59         CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, NULL);
000006  4601              MOV      r1,r0
000008  2200              MOVS     r2,#0
00000a  4808              LDR      r0,|L5.44|
00000c  f7fffffe          BL       CLK_SetModuleClock
;;;60     
;;;61         /* CKO = clock source / 2^(u32ClkDiv + 1) */
;;;62         CLK->CLKOCTL = (CLK->CLKOCTL & ~(CLK_CLKOCTL_FREQSEL_Msk | CLK_CLKOCTL_DIV1EN_Msk))
000010  4807              LDR      r0,|L5.48|
000012  6a01              LDR      r1,[r0,#0x20]
000014  222f              MOVS     r2,#0x2f
000016  4391              BICS     r1,r1,r2
000018  4329              ORRS     r1,r1,r5
00001a  0162              LSLS     r2,r4,#5
00001c  4311              ORRS     r1,r1,r2
00001e  6201              STR      r1,[r0,#0x20]
;;;63                         | ((u32ClkDiv) << CLK_CLKOCTL_FREQSEL_Pos)
;;;64                         | ((u32ClkDivBy1En) << CLK_CLKOCTL_DIV1EN_Pos);
;;;65     
;;;66         /* Enable CKO clock source */
;;;67         CLK->CLKOCTL |= CLK_CLKOCTL_CLKOEN_Msk;
000020  6a01              LDR      r1,[r0,#0x20]
000022  2210              MOVS     r2,#0x10
000024  4311              ORRS     r1,r1,r2
000026  6201              STR      r1,[r0,#0x20]
;;;68     }
000028  bd30              POP      {r4,r5,pc}
;;;69     
                          ENDP

00002a  0000              DCW      0x0000
                  |L5.44|
                          DCD      0x48bc0006
                  |L5.48|
                          DCD      0x50000240

                          AREA ||i.CLK_EnableModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_EnableModuleClock PROC
;;;339      */
;;;340    void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
000000  0f81              LSRS     r1,r0,#30
;;;341    {
;;;342        *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4))  |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
000002  008a              LSLS     r2,r1,#2
000004  4904              LDR      r1,|L6.24|
000006  1851              ADDS     r1,r2,r1
000008  684a              LDR      r2,[r1,#4]
00000a  06c3              LSLS     r3,r0,#27
00000c  0edb              LSRS     r3,r3,#27
00000e  2001              MOVS     r0,#1
000010  4098              LSLS     r0,r0,r3
000012  4302              ORRS     r2,r2,r0
000014  604a              STR      r2,[r1,#4]
;;;343    }
000016  4770              BX       lr
;;;344    
                          ENDP

                  |L6.24|
                          DCD      0x50000200

                          AREA ||i.CLK_EnableSysTick||, CODE, READONLY, ALIGN=2

                  CLK_EnableSysTick PROC
;;;408      */
;;;409    void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
000000  b570              PUSH     {r4-r6,lr}
;;;410    {
;;;411        SysTick->CTRL=0;
000002  4a0d              LDR      r2,|L7.56|
000004  2300              MOVS     r3,#0
000006  6113              STR      r3,[r2,#0x10]
;;;412        if( u32ClkSrc== CLK_SYSTICK_SRC_HCLK )    /* Set System Tick clock source */
;;;413            SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
000008  2404              MOVS     r4,#4
00000a  2820              CMP      r0,#0x20              ;412
00000c  d00f              BEQ      |L7.46|
;;;414        else
;;;415        {
;;;416            SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
00000e  6915              LDR      r5,[r2,#0x10]
000010  43a5              BICS     r5,r5,r4
000012  6115              STR      r5,[r2,#0x10]
;;;417            CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
000014  4d09              LDR      r5,|L7.60|
000016  692c              LDR      r4,[r5,#0x10]
000018  2618              MOVS     r6,#0x18
00001a  43b4              BICS     r4,r4,r6
00001c  4304              ORRS     r4,r4,r0
00001e  612c              STR      r4,[r5,#0x10]
                  |L7.32|
;;;418        }
;;;419        SysTick->LOAD  = u32Count;                /* Set System Tick reload value */
000020  6151              STR      r1,[r2,#0x14]
;;;420        SysTick->VAL = 0;                         /* Clear System Tick current value and counter flag  */
000022  6193              STR      r3,[r2,#0x18]
;;;421        SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; /* Set System Tick counter enabled */
000024  6910              LDR      r0,[r2,#0x10]
000026  2101              MOVS     r1,#1
000028  4308              ORRS     r0,r0,r1
00002a  6110              STR      r0,[r2,#0x10]
;;;422    }
00002c  bd70              POP      {r4-r6,pc}
                  |L7.46|
00002e  6910              LDR      r0,[r2,#0x10]         ;413
000030  4320              ORRS     r0,r0,r4              ;413
000032  6110              STR      r0,[r2,#0x10]         ;413
000034  e7f4              B        |L7.32|
;;;423    
                          ENDP

000036  0000              DCW      0x0000
                  |L7.56|
                          DCD      0xe000e000
                  |L7.60|
                          DCD      0x50000200

                          AREA ||i.CLK_EnableXtalRC||, CODE, READONLY, ALIGN=2

                  CLK_EnableXtalRC PROC
;;;299      */
;;;300    void CLK_EnableXtalRC(uint32_t u32ClkMask)
000000  4902              LDR      r1,|L8.12|
;;;301    {
;;;302        CLK->PWRCTL |= u32ClkMask;
000002  680a              LDR      r2,[r1,#0]
000004  4302              ORRS     r2,r2,r0
000006  600a              STR      r2,[r1,#0]
;;;303    }
000008  4770              BX       lr
;;;304    
                          ENDP

00000a  0000              DCW      0x0000
                  |L8.12|
                          DCD      0x50000200

                          AREA ||i.CLK_GetCPUFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetCPUFreq PROC
;;;155      */
;;;156    uint32_t CLK_GetCPUFreq(void)
000000  b510              PUSH     {r4,lr}
;;;157    {
;;;158        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;159        return SystemCoreClock;
000006  4801              LDR      r0,|L9.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;160    }
00000a  bd10              POP      {r4,pc}
;;;161    
                          ENDP

                  |L9.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetHCLKFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetHCLKFreq PROC
;;;131      */
;;;132    uint32_t CLK_GetHCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;133    {
;;;134        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;135        return SystemCoreClock;
000006  4801              LDR      r0,|L10.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;136    }
00000a  bd10              POP      {r4,pc}
;;;137    
                          ENDP

                  |L10.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetHXTFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetHXTFreq PROC
;;;105      */
;;;106    uint32_t CLK_GetHXTFreq(void)
000000  4804              LDR      r0,|L11.20|
;;;107    {
;;;108        if ( ((CLK->PWRCTL & CLK_PWRCTL_XTLEN_Msk) >> CLK_PWRCTL_XTLEN_Pos) == 0x01 )
000002  6800              LDR      r0,[r0,#0]
000004  0780              LSLS     r0,r0,#30
000006  0f80              LSRS     r0,r0,#30
000008  2801              CMP      r0,#1
00000a  d001              BEQ      |L11.16|
;;;109            return __HXT;
;;;110        else
;;;111            return 0;
00000c  2000              MOVS     r0,#0
;;;112    }
00000e  4770              BX       lr
                  |L11.16|
000010  4801              LDR      r0,|L11.24|
000012  4770              BX       lr
;;;113    
                          ENDP

                  |L11.20|
                          DCD      0x50000200
                  |L11.24|
                          DCD      0x00b71b00

                          AREA ||i.CLK_GetLXTFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetLXTFreq PROC
;;;118      */
;;;119    uint32_t CLK_GetLXTFreq(void)
000000  4805              LDR      r0,|L12.24|
;;;120    {
;;;121        if ( ((CLK->PWRCTL & CLK_PWRCTL_XTLEN_Msk) >> CLK_PWRCTL_XTLEN_Pos) == 0x02 )
000002  6800              LDR      r0,[r0,#0]
000004  0780              LSLS     r0,r0,#30
000006  0f80              LSRS     r0,r0,#30
000008  2802              CMP      r0,#2
00000a  d001              BEQ      |L12.16|
;;;122            return __LXT;
;;;123        else
;;;124            return 0;
00000c  2000              MOVS     r0,#0
;;;125    }
00000e  4770              BX       lr
                  |L12.16|
000010  2001              MOVS     r0,#1                 ;122
000012  03c0              LSLS     r0,r0,#15             ;122
000014  4770              BX       lr
;;;126    
                          ENDP

000016  0000              DCW      0x0000
                  |L12.24|
                          DCD      0x50000200

                          AREA ||i.CLK_GetPCLKFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetPCLKFreq PROC
;;;144      */
;;;145    uint32_t CLK_GetPCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;146    {
;;;147        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;148        return SystemCoreClock;
000006  4801              LDR      r0,|L13.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;149    }
00000a  bd10              POP      {r4,pc}
;;;150    
                          ENDP

                  |L13.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_Idle||, CODE, READONLY, ALIGN=2

                  CLK_Idle PROC
;;;92       */
;;;93     void CLK_Idle(void)
000000  4803              LDR      r0,|L14.16|
;;;94     {
;;;95         // disable system power-down feature
;;;96         CLK->PWRCTL &= ~(CLK_PWRCTL_PDEN_Msk);
000002  6801              LDR      r1,[r0,#0]
000004  2280              MOVS     r2,#0x80
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;97         // execute Wait For Interrupt; Enter idle mode since CLK_PWRCTL_PDEN_Msk is 0
;;;98         __WFI();
00000a  bf30              WFI      
;;;99     }
00000c  4770              BX       lr
;;;100    
                          ENDP

00000e  0000              DCW      0x0000
                  |L14.16|
                          DCD      0x50000200

                          AREA ||i.CLK_PowerDown||, CODE, READONLY, ALIGN=2

                  CLK_PowerDown PROC
;;;75       */
;;;76     void CLK_PowerDown(void)
000000  4807              LDR      r0,|L15.32|
;;;77     {
;;;78         // enable M0 register SCR[SEVONPEND] and SCR[SLEEPDEEP]
;;;79         SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SEVONPEND_Msk);
000002  6901              LDR      r1,[r0,#0x10]
000004  2214              MOVS     r2,#0x14
000006  4311              ORRS     r1,r1,r2
000008  6101              STR      r1,[r0,#0x10]
;;;80         // clear interrupt status and enable wake up interrupt
;;;81         CLK->PWRCTL |= (CLK_PWRCTL_PDWKIF_Msk | CLK_PWRCTL_PDWKIEN_Msk);
00000a  4806              LDR      r0,|L15.36|
00000c  6801              LDR      r1,[r0,#0]
00000e  2260              MOVS     r2,#0x60
000010  4311              ORRS     r1,r1,r2
000012  6001              STR      r1,[r0,#0]
;;;82         // enable system power-down feature
;;;83         CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk);
000014  6801              LDR      r1,[r0,#0]
000016  2280              MOVS     r2,#0x80
000018  4311              ORRS     r1,r1,r2
00001a  6001              STR      r1,[r0,#0]
;;;84         // execute Wait For Interrupt; Enter power-down mode since CLK_PWRCTL_PDEN_Msk is 1
;;;85         __WFI();
00001c  bf30              WFI      
;;;86     }
00001e  4770              BX       lr
;;;87     
                          ENDP

                  |L15.32|
                          DCD      0xe000ed00
                  |L15.36|
                          DCD      0x50000200

                          AREA ||i.CLK_SetCoreClock||, CODE, READONLY, ALIGN=2

                          REQUIRE _printf_percent
                          REQUIRE _printf_d
                          REQUIRE _printf_int_dec
                  CLK_SetCoreClock PROC
;;;166      */
;;;167    uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
000000  b570              PUSH     {r4-r6,lr}
;;;168    {
;;;169        uint32_t u32Div;
;;;170    
;;;171        if ((u32Hclk <= __HIRC) && (u32Hclk > 0))
000002  4a0f              LDR      r2,|L16.64|
000004  1e41              SUBS     r1,r0,#1
;;;172        {
;;;173            u32Div = __HIRC / u32Hclk;
;;;174            if (__HIRC % u32Hclk != 0)
;;;175                u32Div++;
;;;176            if (u32Div > 16)
;;;177            {
;;;178                printf("ERROR: CLK_SetCoreClock(): HCLK divider (%d) cannot > 16 !!\n", u32Div);
;;;179                return SystemCoreClock; // Don't change HCLK. Return current HCLK.
000006  4d0f              LDR      r5,|L16.68|
000008  4291              CMP      r1,r2                 ;171
;;;180            }
;;;181        }
;;;182        else
;;;183        {
;;;184            printf("ERROR: CLK_SetCoreClock(): Invalid HCLK frequency %d !!\n", u32Hclk);
00000a  4601              MOV      r1,r0
00000c  d80d              BHI      |L16.42|
00000e  1c50              ADDS     r0,r2,#1              ;173
000010  f7fffffe          BL       __aeabi_uidivmod
000014  4604              MOV      r4,r0                 ;173
000016  2900              CMP      r1,#0                 ;174
000018  d000              BEQ      |L16.28|
00001a  1c44              ADDS     r4,r0,#1              ;175
                  |L16.28|
00001c  2c10              CMP      r4,#0x10              ;176
00001e  d906              BLS      |L16.46|
000020  4621              MOV      r1,r4                 ;178
000022  a009              ADR      r0,|L16.72|
                  |L16.36|
000024  f7fffffe          BL       __2printf
000028  e008              B        |L16.60|
                  |L16.42|
00002a  a017              ADR      r0,|L16.136|
;;;185            return SystemCoreClock; // Don't change HCLK. Return current HCLK.
00002c  e7fa              B        |L16.36|
                  |L16.46|
;;;186        }
;;;187        CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
00002e  2010              MOVS     r0,#0x10
000030  f7fffffe          BL       CLK_WaitClockReady
;;;188        CLK_SetHCLK(CLK_HCLK_SRC_HIRC, CLK_CLKDIV_HCLK(u32Div));
000034  1e61              SUBS     r1,r4,#1
000036  2003              MOVS     r0,#3
000038  f7fffffe          BL       CLK_SetHCLK
                  |L16.60|
;;;189        return SystemCoreClock;
00003c  6828              LDR      r0,[r5,#0]  ; SystemCoreClock
;;;190    }
00003e  bd70              POP      {r4-r6,pc}
;;;191    
                          ENDP

                  |L16.64|
                          DCD      0x02dc6bff
                  |L16.68|
                          DCD      SystemCoreClock
                  |L16.72|
000048  4552524f          DCB      "ERROR: CLK_SetCoreClock(): HCLK divider (%d) cannot > 1"
00004c  523a2043
000050  4c4b5f53
000054  6574436f
000058  7265436c
00005c  6f636b28
000060  293a2048
000064  434c4b20
000068  64697669
00006c  64657220
000070  28256429
000074  2063616e
000078  6e6f7420
00007c  3e2031  
00007f  36202121          DCB      "6 !!\n",0
000083  0a00    
000085  00                DCB      0
000086  00                DCB      0
000087  00                DCB      0
                  |L16.136|
000088  4552524f          DCB      "ERROR: CLK_SetCoreClock(): Invalid HCLK frequency %d !!"
00008c  523a2043
000090  4c4b5f53
000094  6574436f
000098  7265436c
00009c  6f636b28
0000a0  293a2049
0000a4  6e76616c
0000a8  69642048
0000ac  434c4b20
0000b0  66726571
0000b4  75656e63
0000b8  79202564
0000bc  202121  
0000bf  0a00              DCB      "\n",0
0000c1  00                DCB      0
0000c2  00                DCB      0
0000c3  00                DCB      0

                          AREA ||i.CLK_SetHCLK||, CODE, READONLY, ALIGN=2

                  CLK_SetHCLK PROC
;;;201      */
;;;202    void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b510              PUSH     {r4,lr}
;;;203    {
;;;204        CLK->CLKDIV  = (CLK->CLKDIV  & ~CLK_CLKDIV_HCLKDIV_Msk)  | u32ClkDiv;
000002  4a09              LDR      r2,|L17.40|
000004  6a13              LDR      r3,[r2,#0x20]
000006  091b              LSRS     r3,r3,#4
000008  011b              LSLS     r3,r3,#4
00000a  430b              ORRS     r3,r3,r1
00000c  6213              STR      r3,[r2,#0x20]
;;;205        CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk) | u32ClkSrc;
00000e  6911              LDR      r1,[r2,#0x10]
000010  0889              LSRS     r1,r1,#2
000012  0089              LSLS     r1,r1,#2
000014  4301              ORRS     r1,r1,r0
000016  6111              STR      r1,[r2,#0x10]
;;;206        CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
000018  6810              LDR      r0,[r2,#0]
00001a  2104              MOVS     r1,#4
00001c  4308              ORRS     r0,r0,r1
00001e  6010              STR      r0,[r2,#0]
;;;207        SystemCoreClockUpdate();
000020  f7fffffe          BL       SystemCoreClockUpdate
;;;208    }
000024  bd10              POP      {r4,pc}
;;;209    
                          ENDP

000026  0000              DCW      0x0000
                  |L17.40|
                          DCD      0x50000200

                          AREA ||i.CLK_SetModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_SetModuleClock PROC
;;;269    
;;;270    void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b5f0              PUSH     {r4-r7,lr}
;;;271    {
;;;272        uint32_t u32tmp=0,u32sel=0,u32div=0;
;;;273    
;;;274        if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
000002  0483              LSLS     r3,r0,#18
000004  0f1d              LSRS     r5,r3,#28
000006  2401              MOVS     r4,#1
000008  4623              MOV      r3,r4
00000a  40ab              LSLS     r3,r3,r5
00000c  461e              MOV      r6,r3
00000e  2b01              CMP      r3,#1
000010  d00c              BEQ      |L18.44|
;;;275            u32div =(uint32_t)&CLK->CLKDIV+((MODULE_CLKDIV(u32ModuleIdx))*4);   // Get register address
000012  03c3              LSLS     r3,r0,#15
000014  0f5b              LSRS     r3,r3,#29
000016  4d0f              LDR      r5,|L18.84|
000018  009b              LSLS     r3,r3,#2
00001a  195b              ADDS     r3,r3,r5
;;;276            u32tmp = *(volatile uint32_t *)(u32div);                            // Get register content value
00001c  681d              LDR      r5,[r3,#0]
;;;277            u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv;
00001e  0587              LSLS     r7,r0,#22
000020  0eff              LSRS     r7,r7,#27
000022  1e76              SUBS     r6,r6,#1
000024  40be              LSLS     r6,r6,r7
000026  43b5              BICS     r5,r5,r6
000028  4315              ORRS     r5,r5,r2
;;;278            *(volatile uint32_t *)(u32div) = u32tmp;
00002a  601d              STR      r5,[r3,#0]
                  |L18.44|
;;;279        }
;;;280    
;;;281        if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
00002c  0142              LSLS     r2,r0,#5
00002e  0ed2              LSRS     r2,r2,#27
000030  4094              LSLS     r4,r4,r2
000032  2c01              CMP      r4,#1
000034  d00d              BEQ      |L18.82|
;;;282            u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4); // Get register address
000036  0082              LSLS     r2,r0,#2
000038  4b06              LDR      r3,|L18.84|
00003a  0f52              LSRS     r2,r2,#29
00003c  0092              LSLS     r2,r2,#2
00003e  3b10              SUBS     r3,r3,#0x10
000040  18d2              ADDS     r2,r2,r3
;;;283            u32tmp = *(volatile uint32_t *)(u32sel);                            // Get register content value
000042  6813              LDR      r3,[r2,#0]
;;;284            u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc;
000044  0280              LSLS     r0,r0,#10
000046  0ec0              LSRS     r0,r0,#27
000048  1e64              SUBS     r4,r4,#1
00004a  4084              LSLS     r4,r4,r0
00004c  43a3              BICS     r3,r3,r4
00004e  430b              ORRS     r3,r3,r1
;;;285            *(volatile uint32_t *)(u32sel) = u32tmp;
000050  6013              STR      r3,[r2,#0]
                  |L18.82|
;;;286        }
;;;287    }
000052  bdf0              POP      {r4-r7,pc}
;;;288    
                          ENDP

                  |L18.84|
                          DCD      0x50000220

                          AREA ||i.CLK_SetPCLK||, CODE, READONLY, ALIGN=2

                  CLK_SetPCLK PROC
;;;221      */
;;;222    void CLK_SetPCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b510              PUSH     {r4,lr}
;;;223    {
;;;224        CLK->CLKDIV  = (CLK->CLKDIV  & ~CLK_CLKDIV_HCLKDIV_Msk)  | u32ClkDiv;
000002  4a09              LDR      r2,|L19.40|
000004  6a13              LDR      r3,[r2,#0x20]
000006  091b              LSRS     r3,r3,#4
000008  011b              LSLS     r3,r3,#4
00000a  430b              ORRS     r3,r3,r1
00000c  6213              STR      r3,[r2,#0x20]
;;;225        CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk) | u32ClkSrc;
00000e  6911              LDR      r1,[r2,#0x10]
000010  0889              LSRS     r1,r1,#2
000012  0089              LSLS     r1,r1,#2
000014  4301              ORRS     r1,r1,r0
000016  6111              STR      r1,[r2,#0x10]
;;;226        CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
000018  6810              LDR      r0,[r2,#0]
00001a  2104              MOVS     r1,#4
00001c  4308              ORRS     r0,r0,r1
00001e  6010              STR      r0,[r2,#0]
;;;227        SystemCoreClockUpdate();
000020  f7fffffe          BL       SystemCoreClockUpdate
;;;228    }
000024  bd10              POP      {r4,pc}
;;;229    
                          ENDP

000026  0000              DCW      0x0000
                  |L19.40|
                          DCD      0x50000200

                          AREA ||i.CLK_SysTickDelay||, CODE, READONLY, ALIGN=2

                          REQUIRE _printf_percent
                          REQUIRE _printf_d
                          REQUIRE _printf_int_dec
                  CLK_SysTickDelay PROC
;;;376      */
;;;377    void CLK_SysTickDelay(uint32_t us)
000000  b570              PUSH     {r4-r6,lr}
;;;378    {
000002  4605              MOV      r5,r0
;;;379        uint32_t delay_tick;
;;;380    
;;;381        delay_tick = us * CyclesPerUs;
000004  4604              MOV      r4,r0
000006  480c              LDR      r0,|L20.56|
000008  6801              LDR      r1,[r0,#0]  ; CyclesPerUs
;;;382        if (delay_tick > SysTick_LOAD_RELOAD_Msk)   // SysTick_LOAD_RELOAD_Msk is 24 bits for NM1120
00000a  480c              LDR      r0,|L20.60|
00000c  434c              MULS     r4,r1,r4              ;381
00000e  4284              CMP      r4,r0
000010  d907              BLS      |L20.34|
;;;383        {
;;;384            printf("ERROR: CLK_SysTickDelay(): the delay tick (%d) cannot > %d !\n", us, SysTick_LOAD_RELOAD_Msk/CyclesPerUs);
000012  f7fffffe          BL       __aeabi_uidivmod
000016  4602              MOV      r2,r0
000018  4629              MOV      r1,r5
00001a  a009              ADR      r0,|L20.64|
00001c  f7fffffe          BL       __2printf
;;;385            return;
;;;386        }
;;;387        SysTick->LOAD = delay_tick;
;;;388        SysTick->VAL  = (0x00);
;;;389        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
;;;390    
;;;391        /* Waiting for down-count to zero */
;;;392        while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
;;;393        SysTick->CTRL = 0;
;;;394    }
000020  bd70              POP      {r4-r6,pc}
                  |L20.34|
000022  4817              LDR      r0,|L20.128|
000024  6144              STR      r4,[r0,#0x14]         ;387
000026  2200              MOVS     r2,#0                 ;388
000028  6182              STR      r2,[r0,#0x18]         ;388
00002a  2105              MOVS     r1,#5                 ;389
00002c  6101              STR      r1,[r0,#0x10]         ;389
                  |L20.46|
00002e  6901              LDR      r1,[r0,#0x10]         ;392
000030  03c9              LSLS     r1,r1,#15             ;392
000032  d5fc              BPL      |L20.46|
000034  6102              STR      r2,[r0,#0x10]         ;393
000036  bd70              POP      {r4-r6,pc}
;;;395    
                          ENDP

                  |L20.56|
                          DCD      CyclesPerUs
                  |L20.60|
                          DCD      0x00ffffff
                  |L20.64|
000040  4552524f          DCB      "ERROR: CLK_SysTickDelay(): the delay tick (%d) cannot >"
000044  523a2043
000048  4c4b5f53
00004c  79735469
000050  636b4465
000054  6c617928
000058  293a2074
00005c  68652064
000060  656c6179
000064  20746963
000068  6b202825
00006c  64292063
000070  616e6e6f
000074  74203e  
000077  20256420          DCB      " %d !\n",0
00007b  210a00  
00007e  00                DCB      0
00007f  00                DCB      0
                  |L20.128|
                          DCD      0xe000e000

                          AREA ||i.CLK_WaitClockReady||, CODE, READONLY, ALIGN=2

                  CLK_WaitClockReady PROC
;;;445      */
;;;446    uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
000000  b510              PUSH     {r4,lr}
;;;447    {
000002  4604              MOV      r4,r0
;;;448        int32_t i32TimeOutCnt=2160000;
000004  4907              LDR      r1,|L21.36|
;;;449    
;;;450        while((CLK->STATUS & u32ClkMask) != u32ClkMask) {
000006  4b08              LDR      r3,|L21.40|
000008  e005              B        |L21.22|
                  |L21.10|
;;;451            if(i32TimeOutCnt-- <= 0)
00000a  460a              MOV      r2,r1
00000c  1e49              SUBS     r1,r1,#1
00000e  2a00              CMP      r2,#0
000010  dc01              BGT      |L21.22|
;;;452                return 0;
000012  2000              MOVS     r0,#0
;;;453        }
;;;454        return 1;
;;;455    }
000014  bd10              POP      {r4,pc}
                  |L21.22|
000016  691a              LDR      r2,[r3,#0x10]         ;450
000018  4620              MOV      r0,r4                 ;450
00001a  4390              BICS     r0,r0,r2              ;450
00001c  d1f5              BNE      |L21.10|
00001e  2001              MOVS     r0,#1                 ;454
000020  bd10              POP      {r4,pc}
;;;456    
                          ENDP

000022  0000              DCW      0x0000
                  |L21.36|
                          DCD      0x0020f580
                  |L21.40|
                          DCD      0x50000240

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\clk.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___5_clk_c_9b5832dc____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___5_clk_c_9b5832dc____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___5_clk_c_9b5832dc____REVSH|
#line 132
|__asm___5_clk_c_9b5832dc____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
