; generated by Component: ARM Compiler 5.04 update 1 (build 49) Tool: ArmCC [5040049]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\eadc.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\eadc.d --cpu=Cortex-M0 --apcs=interwork -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\NM1120\Include -I..\..\..\..\Library\StdDriver\inc -I.\source -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\eadc.crf ..\..\..\..\Library\StdDriver\src\eadc.c]
                          THUMB

                          AREA ||i.EADC_Close||, CODE, READONLY, ALIGN=2

                  EADC_Close PROC
;;;44       */
;;;45     void EADC_Close(EADC_T *eadc)
000000  b510              PUSH     {r4,lr}
;;;46     {
;;;47         eadc->CTL = eadc->CTL
000002  6a01              LDR      r1,[r0,#0x20]
000004  4a03              LDR      r2,|L1.20|
000006  4311              ORRS     r1,r1,r2
000008  6201              STR      r1,[r0,#0x20]
;;;48                  | (EADC_EADC0_7 << EADC_CTL_ADC0CHSEL_Pos)                 // Switching to channel Vss to save power
;;;49                  | ((EADC_EADC1_7-EADC_EADC1_0) << EADC_CTL_ADC1CHSEL_Pos)  // Switching to channel Vss to save power
;;;50                  & (~EADC_CTL_ADCEN_Msk);
;;;51         SYS_ResetModule(EADC_RST);
00000a  2001              MOVS     r0,#1
00000c  0700              LSLS     r0,r0,#28
00000e  f7fffffe          BL       SYS_ResetModule
;;;52     }
000012  bd10              POP      {r4,pc}
;;;53     
                          ENDP

                  |L1.20|
                          DCD      0x07070000

                          AREA ||i.EADC_ConfigSampleModule||, CODE, READONLY, ALIGN=1

                  EADC_ConfigSampleModule PROC
;;;113      */
;;;114    void EADC_ConfigSampleModule(EADC_T *eadc,
000000  b510              PUSH     {r4,lr}
;;;115                                 uint32_t u32ModuleNum,
;;;116                                 uint32_t u32TriggerSrc,
;;;117                                 uint32_t u32Channel)
;;;118    {
;;;119        if (u32ModuleNum <= EADC_EADC0_7)
000002  2907              CMP      r1,#7
000004  d815              BHI      |L2.50|
;;;120        {
;;;121            eadc->CTL = (eadc->CTL & ~EADC_CTL_ADC0CHSEL_Msk) | (u32ModuleNum << EADC_CTL_ADC0CHSEL_Pos);
000006  6a03              LDR      r3,[r0,#0x20]
000008  2407              MOVS     r4,#7
00000a  0424              LSLS     r4,r4,#16
00000c  43a3              BICS     r3,r3,r4
00000e  0409              LSLS     r1,r1,#16
000010  430b              ORRS     r3,r3,r1
000012  6203              STR      r3,[r0,#0x20]
;;;122            if (u32TriggerSrc == EADC_SOFTWARE_TRIGGER)
;;;123                eadc->CTL &= ~EADC_CTL_ADC0HWTRGEN_Msk;
000014  2104              MOVS     r1,#4
000016  2a00              CMP      r2,#0                 ;122
000018  d008              BEQ      |L2.44|
;;;124            else
;;;125            {
;;;126                eadc->TRGSOR = (eadc->TRGSOR & ~(EADC_TRGSOR_ADC0TRGSOR_Msk | EADC_TRGSOR_ADC0STADCSEL_Msk | EADC_TRGSOR_ADC0PWMTRGSEL_Msk))
00001a  6a43              LDR      r3,[r0,#0x24]
00001c  0a1b              LSRS     r3,r3,#8
00001e  021b              LSLS     r3,r3,#8
000020  4313              ORRS     r3,r3,r2
000022  6243              STR      r3,[r0,#0x24]
;;;127                             | (u32TriggerSrc << EADC_TRGSOR_ADC0TRGSOR_Pos);
;;;128                eadc->CTL |= EADC_CTL_ADC0HWTRGEN_Msk;
000024  6a02              LDR      r2,[r0,#0x20]
000026  430a              ORRS     r2,r2,r1
                  |L2.40|
000028  6202              STR      r2,[r0,#0x20]
                  |L2.42|
;;;129            }
;;;130        }
;;;131        else if (u32ModuleNum <= EADC_EADC1_7)
;;;132        {
;;;133            eadc->CTL = (eadc->CTL & ~EADC_CTL_ADC1CHSEL_Msk) | ((u32ModuleNum - EADC_EADC1_0) << EADC_CTL_ADC1CHSEL_Pos);
;;;134            if (u32TriggerSrc == EADC_SOFTWARE_TRIGGER)
;;;135                eadc->CTL &= ~EADC_CTL_ADC1HWTRGEN_Msk;
;;;136            else
;;;137            {
;;;138                eadc->TRGSOR = (eadc->TRGSOR & ~(EADC_TRGSOR_ADC1TRGSOR_Msk | EADC_TRGSOR_ADC1STADCSEL_Msk | EADC_TRGSOR_ADC1PWMTRGSEL_Msk))
;;;139                             | (u32TriggerSrc << EADC_TRGSOR_ADC1TRGSOR_Pos);
;;;140                eadc->CTL |= EADC_CTL_ADC1HWTRGEN_Msk;
;;;141            }
;;;142        }
;;;143    }
00002a  bd10              POP      {r4,pc}
                  |L2.44|
00002c  6a02              LDR      r2,[r0,#0x20]         ;123
00002e  438a              BICS     r2,r2,r1              ;123
000030  e7fa              B        |L2.40|
                  |L2.50|
000032  290f              CMP      r1,#0xf               ;131
000034  d8f9              BHI      |L2.42|
000036  6a03              LDR      r3,[r0,#0x20]         ;133
000038  2407              MOVS     r4,#7                 ;133
00003a  0624              LSLS     r4,r4,#24             ;133
00003c  43a3              BICS     r3,r3,r4              ;133
00003e  241f              MOVS     r4,#0x1f              ;133
000040  0609              LSLS     r1,r1,#24             ;133
000042  06e4              LSLS     r4,r4,#27             ;133
000044  1909              ADDS     r1,r1,r4              ;133
000046  430b              ORRS     r3,r3,r1              ;133
000048  6203              STR      r3,[r0,#0x20]         ;133
00004a  2301              MOVS     r3,#1                 ;135
00004c  029b              LSLS     r3,r3,#10             ;135
00004e  2a00              CMP      r2,#0                 ;134
000050  d00a              BEQ      |L2.104|
000052  6a41              LDR      r1,[r0,#0x24]         ;138
000054  24ff              MOVS     r4,#0xff              ;138
000056  0424              LSLS     r4,r4,#16             ;138
000058  43a1              BICS     r1,r1,r4              ;138
00005a  0412              LSLS     r2,r2,#16             ;138
00005c  4311              ORRS     r1,r1,r2              ;138
00005e  6241              STR      r1,[r0,#0x24]         ;138
000060  6a01              LDR      r1,[r0,#0x20]         ;140
000062  4319              ORRS     r1,r1,r3              ;140
                  |L2.100|
000064  6201              STR      r1,[r0,#0x20]         ;140
000066  bd10              POP      {r4,pc}
                  |L2.104|
000068  6a01              LDR      r1,[r0,#0x20]         ;135
00006a  4399              BICS     r1,r1,r3              ;135
00006c  e7fa              B        |L2.100|
;;;144    
                          ENDP


                          AREA ||i.EADC_DisableAllPWMTrigger||, CODE, READONLY, ALIGN=1

                  EADC_DisableAllPWMTrigger PROC
;;;293      */
;;;294    void EADC_DisableAllPWMTrigger(EADC_T *eadc, uint32_t u32ModuleNum)
000000  b500              PUSH     {lr}
;;;295    {
;;;296        EADC_DisablePWMTrigger(eadc, u32ModuleNum, NULL, NULL);
000002  2300              MOVS     r3,#0
000004  461a              MOV      r2,r3
000006  f7fffffe          BL       EADC_DisablePWMTrigger
;;;297    }
00000a  bd00              POP      {pc}
;;;298    
                          ENDP


                          AREA ||i.EADC_DisablePWMTrigger||, CODE, READONLY, ALIGN=1

                  EADC_DisablePWMTrigger PROC
;;;267      */
;;;268    void EADC_DisablePWMTrigger(EADC_T *eadc,
000000  2900              CMP      r1,#0
;;;269                                uint32_t u32ModuleNum,
;;;270                                uint32_t u32Source,
;;;271                                uint32_t u32Param)
;;;272    {
000002  d00c              BEQ      |L4.30|
;;;273        if (u32ModuleNum == EADC_EADC0)
;;;274        {
;;;275            eadc->TRGSOR = eadc->TRGSOR & ~(EADC_TRGSOR_ADC0TRGSOR_Msk | EADC_TRGSOR_ADC0PWMTRGSEL_Msk);
;;;276            eadc->CTL &= ~EADC_CTL_ADC0HWTRGEN_Msk;
;;;277        }
;;;278        else if (u32ModuleNum == EADC_EADC1)
000004  2908              CMP      r1,#8
000006  d109              BNE      |L4.28|
;;;279        {
;;;280            eadc->TRGSOR = eadc->TRGSOR & ~(EADC_TRGSOR_ADC1TRGSOR_Msk | EADC_TRGSOR_ADC1PWMTRGSEL_Msk);
000008  6a41              LDR      r1,[r0,#0x24]
00000a  223f              MOVS     r2,#0x3f
00000c  0412              LSLS     r2,r2,#16
00000e  4391              BICS     r1,r1,r2
000010  6241              STR      r1,[r0,#0x24]
;;;281            eadc->CTL &= ~EADC_CTL_ADC1HWTRGEN_Msk;
000012  6a01              LDR      r1,[r0,#0x20]
000014  2201              MOVS     r2,#1
000016  0292              LSLS     r2,r2,#10
                  |L4.24|
000018  4391              BICS     r1,r1,r2              ;276
00001a  6201              STR      r1,[r0,#0x20]         ;276
                  |L4.28|
;;;282        }
;;;283    }
00001c  4770              BX       lr
                  |L4.30|
00001e  6a41              LDR      r1,[r0,#0x24]         ;275
000020  0989              LSRS     r1,r1,#6              ;275
000022  0189              LSLS     r1,r1,#6              ;275
000024  6241              STR      r1,[r0,#0x24]         ;275
000026  6a01              LDR      r1,[r0,#0x20]         ;276
000028  2204              MOVS     r2,#4                 ;276
00002a  e7f5              B        |L4.24|
;;;284    
                          ENDP


                          AREA ||i.EADC_DisableWCMP||, CODE, READONLY, ALIGN=1

                  EADC_DisableWCMP PROC
;;;304      */
;;;305    void EADC_DisableWCMP(EADC_T *eadc)
000000  6b41              LDR      r1,[r0,#0x34]
;;;306    {
;;;307        eadc->WCMPCTL &= ~EADC_WCMPCTL_WCMPEN_Msk;
000002  0849              LSRS     r1,r1,#1
000004  0049              LSLS     r1,r1,#1
000006  6341              STR      r1,[r0,#0x34]
;;;308    }
000008  4770              BX       lr
;;;309    
                          ENDP


                          AREA ||i.EADC_EnablePWMTrigger||, CODE, READONLY, ALIGN=1

                  EADC_EnablePWMTrigger PROC
;;;236      */
;;;237    void EADC_EnablePWMTrigger(EADC_T *eadc,
000000  2900              CMP      r1,#0
;;;238                               uint32_t u32ModuleNum,
;;;239                               uint32_t u32Source,
;;;240                               uint32_t u32Param)
;;;241    {
000002  d00e              BEQ      |L6.34|
;;;242        if (u32ModuleNum == EADC_EADC0)
;;;243        {
;;;244            eadc->TRGSOR = (eadc->TRGSOR & ~(EADC_TRGSOR_ADC0TRGSOR_Msk | EADC_TRGSOR_ADC0STADCSEL_Msk | EADC_TRGSOR_ADC0PWMTRGSEL_Msk))
;;;245                         | (u32Source << EADC_TRGSOR_ADC0TRGSOR_Pos);
;;;246            eadc->CTL |= EADC_CTL_ADC0HWTRGEN_Msk;
;;;247        }
;;;248        else if (u32ModuleNum == EADC_EADC1)
000004  2908              CMP      r1,#8
000006  d10b              BNE      |L6.32|
;;;249        {
;;;250            eadc->TRGSOR = (eadc->TRGSOR & ~(EADC_TRGSOR_ADC1TRGSOR_Msk | EADC_TRGSOR_ADC1STADCSEL_Msk | EADC_TRGSOR_ADC1PWMTRGSEL_Msk))
000008  6a41              LDR      r1,[r0,#0x24]
00000a  23ff              MOVS     r3,#0xff
00000c  041b              LSLS     r3,r3,#16
00000e  4399              BICS     r1,r1,r3
000010  0412              LSLS     r2,r2,#16
000012  4311              ORRS     r1,r1,r2
000014  6241              STR      r1,[r0,#0x24]
;;;251                         | (u32Source << EADC_TRGSOR_ADC1TRGSOR_Pos);
;;;252            eadc->CTL |= EADC_CTL_ADC1HWTRGEN_Msk;
000016  6a01              LDR      r1,[r0,#0x20]
000018  2201              MOVS     r2,#1
00001a  0292              LSLS     r2,r2,#10
                  |L6.28|
00001c  4311              ORRS     r1,r1,r2              ;246
00001e  6201              STR      r1,[r0,#0x20]         ;246
                  |L6.32|
;;;253        }
;;;254    }
000020  4770              BX       lr
                  |L6.34|
000022  6a41              LDR      r1,[r0,#0x24]         ;244
000024  0a09              LSRS     r1,r1,#8              ;244
000026  0209              LSLS     r1,r1,#8              ;244
000028  4311              ORRS     r1,r1,r2              ;244
00002a  6241              STR      r1,[r0,#0x24]         ;244
00002c  6a01              LDR      r1,[r0,#0x20]         ;246
00002e  2204              MOVS     r2,#4                 ;246
000030  e7f4              B        |L6.28|
;;;255    
                          ENDP


                          AREA ||i.EADC_EnableWCMP||, CODE, READONLY, ALIGN=1

                  EADC_EnableWCMP PROC
;;;328      */
;;;329    void EADC_EnableWCMP(EADC_T *eadc,
000000  b570              PUSH     {r4-r6,lr}
000002  9d05              LDR      r5,[sp,#0x14]
000004  9c04              LDR      r4,[sp,#0x10]
000006  6b46              LDR      r6,[r0,#0x34]
000008  0876              LSRS     r6,r6,#1
00000a  0076              LSLS     r6,r6,#1
00000c  6346              STR      r6,[r0,#0x34]
;;;330                  uint32_t u32HighBund,
;;;331                  uint32_t u32LowBund,
;;;332                  uint32_t u32FlagEN,
;;;333                  uint32_t u32MatchCount,
;;;334                  uint32_t u32FlagCTL)
;;;335    {
;;;336        // MUST disable WCMP first to reset internal compare match counter.
;;;337        EADC_DisableWCMP(eadc);
;;;338    
;;;339        eadc->WCMPDAT = ((u32HighBund & 0xFFF) << EADC_WCMPDAT_CMPUPDAT_Pos)
00000e  0509              LSLS     r1,r1,#20
000010  0909              LSRS     r1,r1,#4
000012  0512              LSLS     r2,r2,#20
000014  0d12              LSRS     r2,r2,#20
000016  4311              ORRS     r1,r1,r2
000018  6381              STR      r1,[r0,#0x38]
;;;340                      | ((u32LowBund  & 0xFFF) << EADC_WCMPDAT_CMPLOWDAT_Pos);
;;;341    
;;;342        if (u32MatchCount == 16)
00001a  2c10              CMP      r4,#0x10
00001c  d100              BNE      |L7.32|
;;;343            u32MatchCount = 0;  // set WCMPMCNT to 0 means count 16.
00001e  2400              MOVS     r4,#0
                  |L7.32|
;;;344        eadc->WCMPCTL = (EADC_WCMPCTL_WCMPEN_Msk)
000020  0721              LSLS     r1,r4,#28
000022  432b              ORRS     r3,r3,r5
000024  0d09              LSRS     r1,r1,#20
000026  430b              ORRS     r3,r3,r1
000028  2101              MOVS     r1,#1
00002a  430b              ORRS     r3,r3,r1
00002c  6343              STR      r3,[r0,#0x34]
;;;345                      | u32FlagEN
;;;346                      | u32FlagCTL
;;;347                      | ((u32MatchCount & 0xF)  << EADC_WCMPCTL_WCMPMCNT_Pos);
;;;348    }
00002e  bd70              POP      {r4-r6,pc}
;;;349    
                          ENDP


                          AREA ||i.EADC_Get_Data_Valid_Flag||, CODE, READONLY, ALIGN=2

                  EADC_Get_Data_Valid_Flag PROC
;;;378      */
;;;379    uint32_t EADC_Get_Data_Valid_Flag(EADC_T *eadc, uint32_t u32ModuleMask)
000000  b510              PUSH     {r4,lr}
;;;380    {
;;;381        uint32_t reg_eadc0, reg_eadc1, valid_flag;
;;;382    
;;;383        reg_eadc0 = EADC->DAT[0];
000002  4809              LDR      r0,|L8.40|
000004  6803              LDR      r3,[r0,#0]
;;;384        reg_eadc1 = EADC->DAT[1];
000006  6842              LDR      r2,[r0,#4]
;;;385    
;;;386        valid_flag = ( ((reg_eadc0 & EADC_DAT0_ADC0VALID_Msk) >> (EADC_DAT0_ADC0VALID_Pos)) |
000008  0418              LSLS     r0,r3,#16
00000a  0f9b              LSRS     r3,r3,#30
00000c  085b              LSRS     r3,r3,#1
00000e  0fc0              LSRS     r0,r0,#31
000010  005b              LSLS     r3,r3,#1
000012  4318              ORRS     r0,r0,r3
000014  0b53              LSRS     r3,r2,#13
000016  2404              MOVS     r4,#4
000018  0f12              LSRS     r2,r2,#28
00001a  4023              ANDS     r3,r3,r4
00001c  08d2              LSRS     r2,r2,#3
00001e  4318              ORRS     r0,r0,r3
000020  00d2              LSLS     r2,r2,#3
000022  4310              ORRS     r0,r0,r2
000024  4008              ANDS     r0,r0,r1
;;;387                       ((reg_eadc0 & EADC_DAT0_ADC1VALID_Msk) >> (EADC_DAT0_ADC1VALID_Pos-1)) |
;;;388                       ((reg_eadc1 & EADC_DAT1_ADC0VALID_Msk) >> (EADC_DAT1_ADC0VALID_Pos-2)) |
;;;389                       ((reg_eadc1 & EADC_DAT1_ADC1VALID_Msk) >> (EADC_DAT1_ADC1VALID_Pos-3)) )
;;;390                     & u32ModuleMask;
;;;391        return (valid_flag);
;;;392    }
000026  bd10              POP      {r4,pc}
;;;393    
                          ENDP

                  |L8.40|
                          DCD      0x400e0000

                          AREA ||i.EADC_Open||, CODE, READONLY, ALIGN=1

                  EADC_Open PROC
;;;33       */
;;;34     void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
000000  6a01              LDR      r1,[r0,#0x20]
;;;35     {
;;;36         eadc->CTL |= EADC_CTL_ADCEN_Msk;
000002  2201              MOVS     r2,#1
000004  4311              ORRS     r1,r1,r2
000006  6201              STR      r1,[r0,#0x20]
;;;37     }
000008  4770              BX       lr
;;;38     
                          ENDP


                          AREA ||i.EADC_ResetWCMPCounter||, CODE, READONLY, ALIGN=1

                  EADC_ResetWCMPCounter PROC
;;;357      */
;;;358    void EADC_ResetWCMPCounter(EADC_T *eadc)
000000  6b41              LDR      r1,[r0,#0x34]
;;;359    {
;;;360        eadc->WCMPCTL &= ~EADC_WCMPCTL_WCMPEN_Msk;
000002  0849              LSRS     r1,r1,#1
000004  0049              LSLS     r1,r1,#1
000006  6341              STR      r1,[r0,#0x34]
;;;361        eadc->WCMPCTL |= EADC_WCMPCTL_WCMPEN_Msk;
000008  6b41              LDR      r1,[r0,#0x34]
00000a  2201              MOVS     r2,#1
00000c  4311              ORRS     r1,r1,r2
00000e  6341              STR      r1,[r0,#0x34]
;;;362    }
000010  4770              BX       lr
;;;363    
                          ENDP


                          AREA ||i.EADC_SetExtendSampleTime||, CODE, READONLY, ALIGN=1

                  EADC_SetExtendSampleTime PROC
;;;194      */
;;;195    void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
000000  6ac1              LDR      r1,[r0,#0x2c]
;;;196    {
;;;197        eadc->SMPCNT = (eadc->SMPCNT & (~EADC_SMPCNT_ADCSMPCNT_Msk)) | ((u32ExtendSampleTime & 0xF) << EADC_SMPCNT_ADCSMPCNT_Pos);
000002  0712              LSLS     r2,r2,#28
000004  0909              LSRS     r1,r1,#4
000006  0109              LSLS     r1,r1,#4
000008  0f12              LSRS     r2,r2,#28
00000a  4311              ORRS     r1,r1,r2
00000c  62c1              STR      r1,[r0,#0x2c]
;;;198    }
00000e  4770              BX       lr
;;;199    
                          ENDP


                          AREA ||i.EADC_SetTriggerDelayTime||, CODE, READONLY, ALIGN=1

                  EADC_SetTriggerDelayTime PROC
;;;157      */
;;;158    void EADC_SetTriggerDelayTime(EADC_T *eadc,
000000  b2d2              UXTB     r2,r2
;;;159                                  uint32_t u32ModuleNum,
;;;160                                  uint32_t u32TriggerDelayTime,
;;;161                                  uint32_t u32DelayClockDivider)
;;;162    {
;;;163        if (u32ModuleNum == EADC_EADC0)
000002  2900              CMP      r1,#0
000004  d009              BEQ      |L12.26|
;;;164            eadc->TRGDLY = (eadc->TRGDLY & (~EADC_TRGDLY_ADC0DELAY_Msk)) | ((u32TriggerDelayTime & 0xFF) << EADC_TRGDLY_ADC0DELAY_Pos);
;;;165        else if (u32ModuleNum == EADC_EADC1)
000006  2908              CMP      r1,#8
000008  d106              BNE      |L12.24|
;;;166            eadc->TRGDLY = (eadc->TRGDLY & (~EADC_TRGDLY_ADC1DELAY_Msk)) | ((u32TriggerDelayTime & 0xFF) << EADC_TRGDLY_ADC1DELAY_Pos);
00000a  6a81              LDR      r1,[r0,#0x28]
00000c  23ff              MOVS     r3,#0xff
00000e  041b              LSLS     r3,r3,#16
000010  4399              BICS     r1,r1,r3
000012  0412              LSLS     r2,r2,#16
                  |L12.20|
000014  4311              ORRS     r1,r1,r2              ;164
000016  6281              STR      r1,[r0,#0x28]         ;164
                  |L12.24|
;;;167    }
000018  4770              BX       lr
                  |L12.26|
00001a  6a81              LDR      r1,[r0,#0x28]         ;164
00001c  0a09              LSRS     r1,r1,#8              ;164
00001e  0209              LSLS     r1,r1,#8              ;164
000020  e7f8              B        |L12.20|
;;;168    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\eadc.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___6_eadc_c_31f612a1____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___6_eadc_c_31f612a1____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___6_eadc_c_31f612a1____REVSH|
#line 132
|__asm___6_eadc_c_31f612a1____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
