; generated by Component: ARM Compiler 5.04 update 1 (build 49) Tool: ArmCC [5040049]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\epwm.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\epwm.d --cpu=Cortex-M0 --apcs=interwork -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\NM1120\Include -I..\..\..\..\Library\StdDriver\inc -I.\source -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\epwm.crf ..\..\..\..\Library\StdDriver\src\epwm.c]
                          THUMB

                          AREA ||i.EPWM_ClearDutyIntFlag||, CODE, READONLY, ALIGN=2

                  EPWM_ClearDutyIntFlag PROC
;;;264     */
;;;265    void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  4a01              LDR      r2,|L1.8|
;;;266    {
;;;267        (epwm)->INTSTS = (EPWM_INTSTS_CMPUIF0_Msk | EPWM_INTSTS_CMPDIF0_Msk) << u32ChannelNum;
000002  408a              LSLS     r2,r2,r1
000004  6582              STR      r2,[r0,#0x58]
;;;268    }
000006  4770              BX       lr
;;;269    
                          ENDP

                  |L1.8|
                          DCD      0x01000100

                          AREA ||i.EPWM_ClearFaultBrakeIntFlag||, CODE, READONLY, ALIGN=1

                  EPWM_ClearFaultBrakeIntFlag PROC
;;;320     */
;;;321    void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
000000  6581              STR      r1,[r0,#0x58]
;;;322    {
;;;323        (epwm)->INTSTS = (u32BrakeSource);
;;;324    }
000002  4770              BX       lr
;;;325    
                          ENDP


                          AREA ||i.EPWM_ClearPeriodIntFlag||, CODE, READONLY, ALIGN=1

                  EPWM_ClearPeriodIntFlag PROC
;;;373     */
;;;374    void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  2101              MOVS     r1,#1
;;;375    {
;;;376        (epwm)->INTSTS = (EPWM_INTSTS_PIF_Msk);
000002  6581              STR      r1,[r0,#0x58]
;;;377    }
000004  4770              BX       lr
;;;378    
                          ENDP


                          AREA ||i.EPWM_ClearZeroIntFlag||, CODE, READONLY, ALIGN=1

                  EPWM_ClearZeroIntFlag PROC
;;;423     */
;;;424    void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  2101              MOVS     r1,#1
;;;425    {
;;;426        (epwm)->INTSTS = (EPWM_INTSTS_CIF_Msk);
000002  0489              LSLS     r1,r1,#18
000004  6581              STR      r1,[r0,#0x58]
;;;427    }
000006  4770              BX       lr
;;;428    
                          ENDP


                          AREA ||i.EPWM_ConfigOutputChannel||, CODE, READONLY, ALIGN=2

                  EPWM_ConfigOutputChannel PROC
;;;34      */
;;;35     uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
000000  b5ff              PUSH     {r0-r7,lr}
;;;36     {
000002  4606              MOV      r6,r0
;;;37         uint32_t i = SystemCoreClock / u32Frequency, j = 0;
000004  4821              LDR      r0,|L5.140|
000006  b083              SUB      sp,sp,#0xc            ;36
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
00000a  4611              MOV      r1,r2
00000c  9001              STR      r0,[sp,#4]
00000e  f7fffffe          BL       __aeabi_uidivmod
000012  2500              MOVS     r5,#0
;;;38         uint16_t  u16Divider = 1;
;;;39         uint16_t u16CNR = 0xFFFF;
000014  4f1e              LDR      r7,|L5.144|
000016  2401              MOVS     r4,#1                 ;38
000018  9000              STR      r0,[sp,#0]
                  |L5.26|
;;;40     
;;;41         for(; u16Divider < 512; u16Divider <<= 1, j++) {  // clk divider could only be 1, 2, 4, 8, 16, 32, 64, 128, 256
;;;42             i = (SystemCoreClock / u32Frequency) / u16Divider;
00001a  4621              MOV      r1,r4
00001c  9800              LDR      r0,[sp,#0]
00001e  f7fffffe          BL       __aeabi_uidivmod
;;;43             // If target value is larger than CNR , need to use a larger divider
;;;44             if(i > (0x10000))
000022  2101              MOVS     r1,#1
000024  0409              LSLS     r1,r1,#16
000026  4288              CMP      r0,r1
000028  d805              BHI      |L5.54|
;;;45                 continue;
;;;46     
;;;47             if(i <= 0x10000) {
;;;48                 if(i == 1)
00002a  2801              CMP      r0,#1
00002c  d001              BEQ      |L5.50|
;;;49                     u16CNR = 1;     // Too fast, and PWM cannot generate expected frequency...
;;;50                 else
;;;51                     u16CNR = i;
00002e  b287              UXTH     r7,r0
000030  e008              B        |L5.68|
                  |L5.50|
000032  2701              MOVS     r7,#1                 ;49
000034  e006              B        |L5.68|
                  |L5.54|
000036  0460              LSLS     r0,r4,#17             ;41
000038  0c04              LSRS     r4,r0,#16             ;41
00003a  2001              MOVS     r0,#1                 ;41
00003c  0240              LSLS     r0,r0,#9              ;41
00003e  1c6d              ADDS     r5,r5,#1              ;41
000040  4284              CMP      r4,r0                 ;41
000042  d3ea              BCC      |L5.26|
                  |L5.68|
000044  4621              MOV      r1,r4                 ;41
;;;52                 break;
;;;53             }
;;;54     
;;;55         }
;;;56         // Store return value here 'cos we're gonna change u8Divider & u16CNR to the real value to fill into register
;;;57         i = SystemCoreClock / (u16Divider * u16CNR);
000046  4379              MULS     r1,r7,r1
000048  9801              LDR      r0,[sp,#4]
00004a  f7fffffe          BL       __aeabi_uidivmod
;;;58     
;;;59         u16CNR -= 1;
;;;60         // convert to real register value
;;;61         u16Divider = j;
00004e  9000              STR      r0,[sp,#0]
000050  1e7f              SUBS     r7,r7,#1              ;57
000052  b2a8              UXTH     r0,r5
000054  b2bc              UXTH     r4,r7                 ;59
;;;62     
;;;63         epwm->CLKDIV = u16Divider;
000056  6070              STR      r0,[r6,#4]
;;;64         epwm->CTL = (epwm->CTL & ~EPWM_CTL_CNTTYPE_Msk) | (EPWM_CTL_CNTMODE_Msk);
000058  68b0              LDR      r0,[r6,#8]
00005a  21ff              MOVS     r1,#0xff
00005c  0040              LSLS     r0,r0,#1
00005e  0840              LSRS     r0,r0,#1
000060  3101              ADDS     r1,#1
000062  4308              ORRS     r0,r0,r1
000064  60b0              STR      r0,[r6,#8]
;;;65         if(u32DutyCycle == 0)
;;;66             epwm->CMPDAT[u32ChannelNum] = 0;
000066  9804              LDR      r0,[sp,#0x10]
000068  9906              LDR      r1,[sp,#0x18]         ;65
00006a  0080              LSLS     r0,r0,#2
00006c  1985              ADDS     r5,r0,r6
00006e  2900              CMP      r1,#0                 ;65
000070  d00a              BEQ      |L5.136|
;;;67         else
;;;68             epwm->CMPDAT[u32ChannelNum] = u32DutyCycle * (u16CNR + 1) / 100;
000072  4608              MOV      r0,r1
000074  1c61              ADDS     r1,r4,#1
000076  4348              MULS     r0,r1,r0
000078  2164              MOVS     r1,#0x64
00007a  f7fffffe          BL       __aeabi_uidivmod
                  |L5.126|
00007e  6268              STR      r0,[r5,#0x24]
;;;69         epwm->PERIOD = u16CNR;
000080  60f4              STR      r4,[r6,#0xc]
;;;70     
;;;71         return(i);
000082  9800              LDR      r0,[sp,#0]
;;;72     }
000084  b007              ADD      sp,sp,#0x1c
000086  bdf0              POP      {r4-r7,pc}
                  |L5.136|
000088  2000              MOVS     r0,#0                 ;66
00008a  e7f8              B        |L5.126|
;;;73     
                          ENDP

                  |L5.140|
                          DCD      SystemCoreClock
                  |L5.144|
                          DCD      0x0000ffff

                          AREA ||i.EPWM_ConfigOutputChannel1||, CODE, READONLY, ALIGN=2

                  EPWM_ConfigOutputChannel1 PROC
;;;81      */
;;;82     void EPWM_ConfigOutputChannel1(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DutyCycle)
000000  2300              MOVS     r3,#0
;;;83     {
;;;84         uint16_t u16CNR;
;;;85         epwm->CLKDIV = 0; // 48Mhz;
000002  6043              STR      r3,[r0,#4]
;;;86     	  u16CNR = PWM_CNR;    // u16CNR = 3Mhz / (2*300) = 5000
;;;87         if(u32DutyCycle == 0)
;;;88             epwm->CMPDAT[u32ChannelNum] = 0;
000004  0089              LSLS     r1,r1,#2
000006  1808              ADDS     r0,r1,r0
000008  2a00              CMP      r2,#0                 ;87
00000a  d004              BEQ      |L6.22|
;;;89         else
;;;90             epwm->CMPDAT[u32ChannelNum] = (u32DutyCycle * (u16CNR + 1))>>12;
00000c  4903              LDR      r1,|L6.28|
00000e  434a              MULS     r2,r1,r2
000010  0b11              LSRS     r1,r2,#12
000012  6241              STR      r1,[r0,#0x24]
;;;91     //     epwm->PERIOD = u16CNR;
;;;92     }
000014  4770              BX       lr
                  |L6.22|
000016  6243              STR      r3,[r0,#0x24]         ;88
000018  4770              BX       lr
;;;93     
                          ENDP

00001a  0000              DCW      0x0000
                  |L6.28|
                          DCD      0x00000781

                          AREA ||i.EPWM_DisableDeadZone||, CODE, READONLY, ALIGN=1

                  EPWM_DisableDeadZone PROC
;;;222     */
;;;223    void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  6883              LDR      r3,[r0,#8]
;;;224    {
;;;225        // every two channels shares the same setting
;;;226        u32ChannelNum >>= 1;
000002  0849              LSRS     r1,r1,#1
;;;227        // enable dead zone
;;;228        epwm->CTL &= ~(EPWM_CTL_DTCNT01_Msk << u32ChannelNum);
000004  2201              MOVS     r2,#1
000006  0612              LSLS     r2,r2,#24
000008  408a              LSLS     r2,r2,r1
00000a  4393              BICS     r3,r3,r2
00000c  6083              STR      r3,[r0,#8]
;;;229    }
00000e  4770              BX       lr
;;;230    
                          ENDP


                          AREA ||i.EPWM_DisableDutyInt||, CODE, READONLY, ALIGN=2

                  EPWM_DisableDutyInt PROC
;;;252     */
;;;253    void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  6d42              LDR      r2,[r0,#0x54]
;;;254    {
;;;255        (epwm)->INTEN &= ~((EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
000002  4b02              LDR      r3,|L8.12|
000004  408b              LSLS     r3,r3,r1
000006  439a              BICS     r2,r2,r3
000008  6542              STR      r2,[r0,#0x54]
;;;256    }
00000a  4770              BX       lr
;;;257    
                          ENDP

                  |L8.12|
                          DCD      0x01000100

                          AREA ||i.EPWM_DisableFaultBrakeInt||, CODE, READONLY, ALIGN=1

                  EPWM_DisableFaultBrakeInt PROC
;;;306     */
;;;307    void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
000000  6d42              LDR      r2,[r0,#0x54]
;;;308    {
;;;309        (epwm)->INTEN &= ~(u32BrakeSource);
000002  438a              BICS     r2,r2,r1
000004  6542              STR      r2,[r0,#0x54]
;;;310    }
000006  4770              BX       lr
;;;311    
                          ENDP


                          AREA ||i.EPWM_DisableOutput||, CODE, READONLY, ALIGN=2

                  EPWM_DisableOutput PROC
;;;184     */
;;;185    void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
000000  b5f0              PUSH     {r4-r7,lr}
;;;186    {
;;;187        uint32_t i;
;;;188        uint32_t field_len = 2;
000002  2602              MOVS     r6,#2
;;;189    
;;;190        for (i=0; i<GPIO_PIN_MAX; i++) {
000004  2000              MOVS     r0,#0
;;;191            if (u32ChannelMask & (1 << i)) {
;;;192                PA->MODE = (PA->MODE & ~(0x3 << (i*field_len))) | (GPIO_MODE_INPUT << (i*field_len));
000006  4d08              LDR      r5,|L10.40|
000008  2701              MOVS     r7,#1                 ;191
                  |L10.10|
00000a  463a              MOV      r2,r7                 ;191
00000c  4082              LSLS     r2,r2,r0              ;191
00000e  420a              TST      r2,r1                 ;191
000010  d006              BEQ      |L10.32|
000012  682c              LDR      r4,[r5,#0]
000014  4602              MOV      r2,r0
000016  4372              MULS     r2,r6,r2
000018  2303              MOVS     r3,#3
00001a  4093              LSLS     r3,r3,r2
00001c  439c              BICS     r4,r4,r3
00001e  602c              STR      r4,[r5,#0]
                  |L10.32|
000020  1c40              ADDS     r0,r0,#1
000022  2807              CMP      r0,#7                 ;190
000024  d3f1              BCC      |L10.10|
;;;193            }
;;;194        }
;;;195    }
000026  bdf0              POP      {r4-r7,pc}
;;;196    
                          ENDP

                  |L10.40|
                          DCD      0x50004000

                          AREA ||i.EPWM_DisablePeriodInt||, CODE, READONLY, ALIGN=1

                  EPWM_DisablePeriodInt PROC
;;;361     */
;;;362    void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  6d41              LDR      r1,[r0,#0x54]
;;;363    {
;;;364        (epwm)->INTEN &= ~(EPWM_INTEN_PIEN_Msk);
000002  0849              LSRS     r1,r1,#1
000004  0049              LSLS     r1,r1,#1
000006  6541              STR      r1,[r0,#0x54]
;;;365    }
000008  4770              BX       lr
;;;366    
                          ENDP


                          AREA ||i.EPWM_DisableZeroInt||, CODE, READONLY, ALIGN=1

                  EPWM_DisableZeroInt PROC
;;;411     */
;;;412    void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  6d41              LDR      r1,[r0,#0x54]
;;;413    {
;;;414        (epwm)->INTEN &= ~(EPWM_INTEN_CIEN_Msk);
000002  2201              MOVS     r2,#1
000004  0492              LSLS     r2,r2,#18
000006  4391              BICS     r1,r1,r2
000008  6541              STR      r1,[r0,#0x54]
;;;415    }
00000a  4770              BX       lr
;;;416    
                          ENDP


                          AREA ||i.EPWM_EnableDeadZone||, CODE, READONLY, ALIGN=1

                  EPWM_EnableDeadZone PROC
;;;205     */
;;;206    void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration)
000000  b530              PUSH     {r4,r5,lr}
;;;207    {
;;;208        // every two channels shares the same setting
;;;209        u32ChannelNum >>= 1;
;;;210        // set duration
;;;211        epwm->DTCTL = (epwm->DTCTL & ~(EPWM_DTCTL_DTCNT01_Msk << (8 * u32ChannelNum))) | (u32Duration << (8 * u32ChannelNum));
000002  6e44              LDR      r4,[r0,#0x64]
000004  0849              LSRS     r1,r1,#1              ;209
000006  00cb              LSLS     r3,r1,#3
000008  25ff              MOVS     r5,#0xff
00000a  409d              LSLS     r5,r5,r3
00000c  43ac              BICS     r4,r4,r5
00000e  409a              LSLS     r2,r2,r3
000010  4314              ORRS     r4,r4,r2
000012  6644              STR      r4,[r0,#0x64]
;;;212        // enable dead zone
;;;213        epwm->CTL |= (EPWM_CTL_DTCNT01_Msk << u32ChannelNum);
000014  6882              LDR      r2,[r0,#8]
000016  2301              MOVS     r3,#1
000018  061b              LSLS     r3,r3,#24
00001a  408b              LSLS     r3,r3,r1
00001c  431a              ORRS     r2,r2,r3
00001e  6082              STR      r2,[r0,#8]
;;;214    }
000020  bd30              POP      {r4,r5,pc}
;;;215    
                          ENDP


                          AREA ||i.EPWM_EnableDutyInt||, CODE, READONLY, ALIGN=1

                  EPWM_EnableDutyInt PROC
;;;240     */
;;;241    void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
000000  6d43              LDR      r3,[r0,#0x54]
;;;242    {
;;;243        (epwm)->INTEN |= (u32IntDutyType << u32ChannelNum);
000002  408a              LSLS     r2,r2,r1
000004  4313              ORRS     r3,r3,r2
000006  6543              STR      r3,[r0,#0x54]
;;;244    }
000008  4770              BX       lr
;;;245    
                          ENDP


                          AREA ||i.EPWM_EnableFaultBrake||, CODE, READONLY, ALIGN=1

                  EPWM_EnableFaultBrake PROC
;;;151     */
;;;152    void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
000000  0611              LSLS     r1,r2,#24
;;;153    {
;;;154        epwm->BRKCTL = (u32LevelMask << EPWM_BRKCTL_BKOD0_Pos) | u32BrakeSource;
000002  4319              ORRS     r1,r1,r3
000004  6601              STR      r1,[r0,#0x60]
;;;155    }
000006  4770              BX       lr
;;;156    
                          ENDP


                          AREA ||i.EPWM_EnableFaultBrakeInt||, CODE, READONLY, ALIGN=1

                  EPWM_EnableFaultBrakeInt PROC
;;;292     */
;;;293    void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
000000  6d42              LDR      r2,[r0,#0x54]
;;;294    {
;;;295        (epwm)->INTEN |= (u32BrakeSource);
000002  430a              ORRS     r2,r2,r1
000004  6542              STR      r2,[r0,#0x54]
;;;296    }
000006  4770              BX       lr
;;;297    
                          ENDP


                          AREA ||i.EPWM_EnableOutput||, CODE, READONLY, ALIGN=2

                  EPWM_EnableOutput PROC
;;;164     */
;;;165    void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
000000  b5f0              PUSH     {r4-r7,lr}
;;;166    {
;;;167        uint32_t i;
;;;168        uint32_t field_len = 2;
000002  2702              MOVS     r7,#2
;;;169    
;;;170        for (i=0; i<GPIO_PIN_MAX; i++) {
000004  2000              MOVS     r0,#0
;;;171            if (u32ChannelMask & (1 << i)) {
;;;172                PA->MODE = (PA->MODE & ~(0x3 << (i*field_len))) | (GPIO_MODE_OUTPUT << (i*field_len));
000006  4e0a              LDR      r6,|L17.48|
000008  2501              MOVS     r5,#1                 ;171
                  |L17.10|
00000a  462a              MOV      r2,r5                 ;171
00000c  4082              LSLS     r2,r2,r0              ;171
00000e  420a              TST      r2,r1                 ;171
000010  d009              BEQ      |L17.38|
000012  6833              LDR      r3,[r6,#0]
000014  4602              MOV      r2,r0
000016  437a              MULS     r2,r7,r2
000018  2403              MOVS     r4,#3
00001a  4094              LSLS     r4,r4,r2
00001c  43a3              BICS     r3,r3,r4
00001e  462c              MOV      r4,r5
000020  4094              LSLS     r4,r4,r2
000022  4323              ORRS     r3,r3,r4
000024  6033              STR      r3,[r6,#0]
                  |L17.38|
000026  1c40              ADDS     r0,r0,#1
000028  2807              CMP      r0,#7                 ;170
00002a  d3ee              BCC      |L17.10|
;;;173            }
;;;174        }
;;;175    }
00002c  bdf0              POP      {r4-r7,pc}
;;;176    
                          ENDP

00002e  0000              DCW      0x0000
                  |L17.48|
                          DCD      0x50004000

                          AREA ||i.EPWM_EnablePeriodInt||, CODE, READONLY, ALIGN=1

                  EPWM_EnablePeriodInt PROC
;;;349     */
;;;350    void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType)
000000  6d41              LDR      r1,[r0,#0x54]
;;;351    {
;;;352        (epwm)->INTEN |= (EPWM_INTEN_PIEN_Msk);
000002  2201              MOVS     r2,#1
000004  4311              ORRS     r1,r1,r2
000006  6541              STR      r1,[r0,#0x54]
;;;353    }
000008  4770              BX       lr
;;;354    
                          ENDP


                          AREA ||i.EPWM_EnableZeroInt||, CODE, READONLY, ALIGN=1

                  EPWM_EnableZeroInt PROC
;;;399     */
;;;400    void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  6d41              LDR      r1,[r0,#0x54]
;;;401    {
;;;402        (epwm)->INTEN |= (EPWM_INTEN_CIEN_Msk);
000002  2201              MOVS     r2,#1
000004  0492              LSLS     r2,r2,#18
000006  4311              ORRS     r1,r1,r2
000008  6541              STR      r1,[r0,#0x54]
;;;403    }
00000a  4770              BX       lr
;;;404    
                          ENDP


                          AREA ||i.EPWM_ForceStop||, CODE, READONLY, ALIGN=1

                  EPWM_ForceStop PROC
;;;127     */
;;;128    void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask)
000000  6882              LDR      r2,[r0,#8]
;;;129    {
;;;130        (epwm)->CTL &= ~u32ChannelMask;
000002  438a              BICS     r2,r2,r1
000004  6082              STR      r2,[r0,#8]
;;;131    }
000006  4770              BX       lr
;;;132    
                          ENDP


                          AREA ||i.EPWM_GetDutyIntFlag||, CODE, READONLY, ALIGN=2

                  EPWM_GetDutyIntFlag PROC
;;;278     */
;;;279    uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  6d80              LDR      r0,[r0,#0x58]
;;;280    {
;;;281        return ((((epwm)->INTSTS & ((EPWM_INTSTS_CMPDIF0_Msk | EPWM_INTSTS_CMPUIF0_Msk) << u32ChannelNum))) ? 1 : 0);
000002  4a03              LDR      r2,|L21.16|
000004  408a              LSLS     r2,r2,r1
000006  4010              ANDS     r0,r0,r2
000008  d000              BEQ      |L21.12|
00000a  2001              MOVS     r0,#1
                  |L21.12|
;;;282    }
00000c  4770              BX       lr
;;;283    
                          ENDP

00000e  0000              DCW      0x0000
                  |L21.16|
                          DCD      0x01000100

                          AREA ||i.EPWM_GetFaultBrakeIntFlag||, CODE, READONLY, ALIGN=1

                  EPWM_GetFaultBrakeIntFlag PROC
;;;336     */
;;;337    uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
000000  6d80              LDR      r0,[r0,#0x58]
;;;338    {
;;;339        return (((epwm)->INTSTS & (u32BrakeSource)) ? 1 : 0);
000002  4008              ANDS     r0,r0,r1
000004  d000              BEQ      |L22.8|
000006  2001              MOVS     r0,#1
                  |L22.8|
;;;340    }
000008  4770              BX       lr
;;;341    
                          ENDP


                          AREA ||i.EPWM_GetPeriodIntFlag||, CODE, READONLY, ALIGN=1

                  EPWM_GetPeriodIntFlag PROC
;;;387     */
;;;388    uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  6d80              LDR      r0,[r0,#0x58]
;;;389    {
;;;390        return ((((epwm)->INTSTS & (EPWM_INTSTS_PIF_Msk))) ? 1 : 0);
000002  07c0              LSLS     r0,r0,#31
000004  0fc0              LSRS     r0,r0,#31
;;;391    }
000006  4770              BX       lr
;;;392    
                          ENDP


                          AREA ||i.EPWM_GetZeroIntFlag||, CODE, READONLY, ALIGN=1

                  EPWM_GetZeroIntFlag PROC
;;;437     */
;;;438    uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
000000  6d80              LDR      r0,[r0,#0x58]
;;;439    {
;;;440        return ((((epwm)->INTSTS & (EPWM_INTSTS_CIF_Msk))) ? 1 : 0);
000002  0340              LSLS     r0,r0,#13
000004  0fc0              LSRS     r0,r0,#31
;;;441    }
000006  4770              BX       lr
;;;442    
                          ENDP


                          AREA ||i.EPWM_Start||, CODE, READONLY, ALIGN=1

                  EPWM_Start PROC
;;;102     */
;;;103    void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask)
000000  6882              LDR      r2,[r0,#8]
;;;104    {
;;;105        (epwm)->CTL |= u32ChannelMask;
000002  430a              ORRS     r2,r2,r1
000004  6082              STR      r2,[r0,#8]
;;;106    }
000006  4770              BX       lr
;;;107    
                          ENDP


                          AREA ||i.EPWM_Stop||, CODE, READONLY, ALIGN=1

                  EPWM_Stop PROC
;;;114     */
;;;115    void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask)
000000  2100              MOVS     r1,#0
;;;116    {
;;;117        (epwm)->PERIOD = 0;
000002  60c1              STR      r1,[r0,#0xc]
;;;118    }
000004  4770              BX       lr
;;;119    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\epwm.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___6_epwm_c_1c70e606____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___6_epwm_c_1c70e606____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___6_epwm_c_1c70e606____REVSH|
#line 132
|__asm___6_epwm_c_1c70e606____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
