; generated by Component: ARM Compiler 5.04 update 1 (build 49) Tool: ArmCC [5040049]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\usci_spi.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\usci_spi.d --cpu=Cortex-M0 --apcs=interwork -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\NM1120\Include -I..\..\..\..\Library\StdDriver\inc -I.\source -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\usci_spi.crf ..\..\..\..\Library\StdDriver\src\usci_spi.c]
                          THUMB

                          AREA ||i.USCI_SPI_ClearIntFlag||, CODE, READONLY, ALIGN=1

                  USCI_SPI_ClearIntFlag PROC
;;;374      */
;;;375    void USCI_SPI_ClearIntFlag(USCI_T *usci, uint32_t u32Mask)
000000  07ca              LSLS     r2,r1,#31
;;;376    {
000002  d002              BEQ      |L1.10|
;;;377        /* Clear slave selection signal inactive interrupt flag */
;;;378        if(u32Mask & USCI_SPI_SSINAIEN_MASK)
;;;379            usci->PROTSTS = USCI_PROTSTS_SSINAIF_Msk;
000004  22ff              MOVS     r2,#0xff
000006  3201              ADDS     r2,#1
000008  6642              STR      r2,[r0,#0x64]
                  |L1.10|
;;;380    
;;;381        /* Clear slave selection signal active interrupt flag */
;;;382        if(u32Mask & USCI_SPI_SSACTIEN_MASK)
00000a  078a              LSLS     r2,r1,#30
00000c  d502              BPL      |L1.20|
;;;383            usci->PROTSTS = USCI_PROTSTS_SSACTIF_Msk;
00000e  2201              MOVS     r2,#1
000010  0252              LSLS     r2,r2,#9
000012  6642              STR      r2,[r0,#0x64]
                  |L1.20|
;;;384    
;;;385        /* Clear slave time-out interrupt flag */
;;;386        if(u32Mask & USCI_SPI_SLVTOIEN_MASK)
000014  074a              LSLS     r2,r1,#29
000016  d501              BPL      |L1.28|
;;;387            usci->PROTSTS = USCI_PROTSTS_SLVTOIF_Msk;
000018  2220              MOVS     r2,#0x20
00001a  6642              STR      r2,[r0,#0x64]
                  |L1.28|
;;;388    
;;;389        /* Clear slave bit count error interrupt flag */
;;;390        if(u32Mask & USCI_SPI_SLVBEIEN_MASK)
00001c  070a              LSLS     r2,r1,#28
00001e  d501              BPL      |L1.36|
;;;391            usci->PROTSTS = USCI_PROTSTS_SLVBEIF_Msk;
000020  2240              MOVS     r2,#0x40
000022  6642              STR      r2,[r0,#0x64]
                  |L1.36|
;;;392    
;;;393        /* Clear TX under run interrupt flag */
;;;394        if(u32Mask & USCI_SPI_TXUDRIEN_MASK)
000024  06ca              LSLS     r2,r1,#27
000026  d502              BPL      |L1.46|
;;;395            usci->BUFSTS = USCI_BUFSTS_TXUDRIF_Msk;
000028  2201              MOVS     r2,#1
00002a  02d2              LSLS     r2,r2,#11
00002c  63c2              STR      r2,[r0,#0x3c]
                  |L1.46|
;;;396    
;;;397        /* Clear RX overrun interrupt flag */
;;;398        if(u32Mask & USCI_SPI_RXOVIEN_MASK)
00002e  068b              LSLS     r3,r1,#26
;;;399            usci->BUFSTS = USCI_BUFSTS_RXOVIF_Msk;
000030  2208              MOVS     r2,#8
000032  2b00              CMP      r3,#0                 ;398
000034  da00              BGE      |L1.56|
000036  63c2              STR      r2,[r0,#0x3c]
                  |L1.56|
;;;400    
;;;401        /* Clear TX start interrupt flag */
;;;402        if(u32Mask & USCI_SPI_TXSTIEN_MASK)
000038  064b              LSLS     r3,r1,#25
00003a  d501              BPL      |L1.64|
;;;403            usci->PROTSTS = USCI_PROTSTS_TXSTIF_Msk;
00003c  2302              MOVS     r3,#2
00003e  6643              STR      r3,[r0,#0x64]
                  |L1.64|
;;;404    
;;;405        /* Clear TX end interrupt flag */
;;;406        if(u32Mask & USCI_SPI_TXENDIEN_MASK)
000040  060b              LSLS     r3,r1,#24
000042  d501              BPL      |L1.72|
;;;407            usci->PROTSTS = USCI_PROTSTS_TXENDIF_Msk;
000044  2304              MOVS     r3,#4
000046  6643              STR      r3,[r0,#0x64]
                  |L1.72|
;;;408    
;;;409        /* Clear RX start interrupt flag */
;;;410        if(u32Mask & USCI_SPI_RXSTIEN_MASK)
000048  05cb              LSLS     r3,r1,#23
00004a  d500              BPL      |L1.78|
;;;411            usci->PROTSTS = USCI_PROTSTS_RXSTIF_Msk;
00004c  6642              STR      r2,[r0,#0x64]
                  |L1.78|
;;;412    
;;;413        /* Clear RX end interrupt flag */
;;;414        if(u32Mask & USCI_SPI_RXENDIEN_MASK)
00004e  0589              LSLS     r1,r1,#22
000050  d501              BPL      |L1.86|
;;;415            usci->PROTSTS = USCI_PROTSTS_RXENDIF_Msk;
000052  2110              MOVS     r1,#0x10
000054  6641              STR      r1,[r0,#0x64]
                  |L1.86|
;;;416    }
000056  4770              BX       lr
;;;417    
                          ENDP


                          AREA ||i.USCI_SPI_ClearRxBuf||, CODE, READONLY, ALIGN=1

                  USCI_SPI_ClearRxBuf PROC
;;;95       */
;;;96     void USCI_SPI_ClearRxBuf(USCI_T *usci)
000000  6b81              LDR      r1,[r0,#0x38]
;;;97     {
;;;98         usci->BUFCTL |= USCI_BUFCTL_RXCLR_Msk;
000002  2201              MOVS     r2,#1
000004  03d2              LSLS     r2,r2,#15
000006  4311              ORRS     r1,r1,r2
000008  6381              STR      r1,[r0,#0x38]
;;;99     }
00000a  4770              BX       lr
;;;100    
                          ENDP


                          AREA ||i.USCI_SPI_ClearTxBuf||, CODE, READONLY, ALIGN=1

                  USCI_SPI_ClearTxBuf PROC
;;;105      */
;;;106    void USCI_SPI_ClearTxBuf(USCI_T *usci)
000000  6b81              LDR      r1,[r0,#0x38]
;;;107    {
;;;108        usci->BUFCTL |= USCI_BUFCTL_TXCLR_Msk;
000002  2280              MOVS     r2,#0x80
000004  4311              ORRS     r1,r1,r2
000006  6381              STR      r1,[r0,#0x38]
;;;109    }
000008  4770              BX       lr
;;;110    
                          ENDP


                          AREA ||i.USCI_SPI_Close||, CODE, READONLY, ALIGN=1

                  USCI_SPI_Close PROC
;;;85       */
;;;86     void USCI_SPI_Close(USCI_T *usci)
000000  6801              LDR      r1,[r0,#0]
;;;87     {
;;;88         usci->CTL &= ~USCI_CTL_FUNMODE_Msk;
000002  08c9              LSRS     r1,r1,#3
000004  00c9              LSLS     r1,r1,#3
000006  6001              STR      r1,[r0,#0]
;;;89     }
000008  4770              BX       lr
;;;90     
                          ENDP


                          AREA ||i.USCI_SPI_DisableAutoSS||, CODE, READONLY, ALIGN=1

                  USCI_SPI_DisableAutoSS PROC
;;;115      */
;;;116    void USCI_SPI_DisableAutoSS(USCI_T *usci)
000000  6dc1              LDR      r1,[r0,#0x5c]
;;;117    {
;;;118        usci->PROTCTL &= ~(USCI_PROTCTL_AUTOSS_Msk | USCI_PROTCTL_SS_Msk);
000002  220c              MOVS     r2,#0xc
000004  4391              BICS     r1,r1,r2
000006  65c1              STR      r1,[r0,#0x5c]
;;;119    }
000008  4770              BX       lr
;;;120    
                          ENDP


                          AREA ||i.USCI_SPI_DisableInt||, CODE, READONLY, ALIGN=1

                  USCI_SPI_DisableInt PROC
;;;248      */
;;;249    void USCI_SPI_DisableInt(USCI_T *usci, uint32_t u32Mask)
000000  b570              PUSH     {r4-r6,lr}
;;;250    {
;;;251        /* Disable slave selection signal inactive interrupt flag */
;;;252        if((u32Mask & USCI_SPI_SSINAIEN_MASK) == USCI_SPI_SSINAIEN_MASK)
000002  07ca              LSLS     r2,r1,#31
000004  d003              BEQ      |L6.14|
;;;253            usci->PROTIEN &= ~USCI_PROTIEN_SSINAIEN_Msk;
000006  6e02              LDR      r2,[r0,#0x60]
000008  0852              LSRS     r2,r2,#1
00000a  0052              LSLS     r2,r2,#1
00000c  6602              STR      r2,[r0,#0x60]
                  |L6.14|
;;;254    
;;;255        /* Disable slave selection signal active interrupt flag */
;;;256        if((u32Mask & USCI_SPI_SSACTIEN_MASK) == USCI_SPI_SSACTIEN_MASK)
00000e  078a              LSLS     r2,r1,#30
;;;257            usci->PROTIEN &= ~USCI_PROTIEN_SSACTIEN_Msk;
000010  2502              MOVS     r5,#2
000012  2a00              CMP      r2,#0                 ;256
000014  da02              BGE      |L6.28|
000016  6e02              LDR      r2,[r0,#0x60]
000018  43aa              BICS     r2,r2,r5
00001a  6602              STR      r2,[r0,#0x60]
                  |L6.28|
;;;258    
;;;259        /* Disable slave time-out interrupt flag */
;;;260        if((u32Mask & USCI_SPI_SLVTOIEN_MASK) == USCI_SPI_SLVTOIEN_MASK)
00001c  074a              LSLS     r2,r1,#29
;;;261            usci->PROTIEN &= ~USCI_PROTIEN_SLVTOIEN_Msk;
00001e  2304              MOVS     r3,#4
000020  2a00              CMP      r2,#0                 ;260
000022  da02              BGE      |L6.42|
000024  6e02              LDR      r2,[r0,#0x60]
000026  439a              BICS     r2,r2,r3
000028  6602              STR      r2,[r0,#0x60]
                  |L6.42|
;;;262    
;;;263        /* Disable slave bit count error interrupt flag */
;;;264        if((u32Mask & USCI_SPI_SLVBEIEN_MASK) == USCI_SPI_SLVBEIEN_MASK)
00002a  070c              LSLS     r4,r1,#28
;;;265            usci->PROTIEN &= ~USCI_PROTIEN_SLVBEIEN_Msk;
00002c  2208              MOVS     r2,#8
00002e  2c00              CMP      r4,#0                 ;264
000030  da02              BGE      |L6.56|
000032  6e04              LDR      r4,[r0,#0x60]
000034  4394              BICS     r4,r4,r2
000036  6604              STR      r4,[r0,#0x60]
                  |L6.56|
;;;266    
;;;267        /* Disable TX under run interrupt flag */
;;;268        if((u32Mask & USCI_SPI_TXUDRIEN_MASK) == USCI_SPI_TXUDRIEN_MASK)
000038  06cc              LSLS     r4,r1,#27
00003a  d503              BPL      |L6.68|
;;;269            usci->BUFCTL &= ~USCI_BUFCTL_TXUDRIEN_Msk;
00003c  6b84              LDR      r4,[r0,#0x38]
00003e  2640              MOVS     r6,#0x40
000040  43b4              BICS     r4,r4,r6
000042  6384              STR      r4,[r0,#0x38]
                  |L6.68|
;;;270    
;;;271        /* Disable RX overrun interrupt flag */
;;;272        if((u32Mask & USCI_SPI_RXOVIEN_MASK) == USCI_SPI_RXOVIEN_MASK)
000044  068c              LSLS     r4,r1,#26
000046  d504              BPL      |L6.82|
;;;273            usci->BUFCTL &= ~USCI_BUFCTL_RXOVIEN_Msk;
000048  6b84              LDR      r4,[r0,#0x38]
00004a  2601              MOVS     r6,#1
00004c  03b6              LSLS     r6,r6,#14
00004e  43b4              BICS     r4,r4,r6
000050  6384              STR      r4,[r0,#0x38]
                  |L6.82|
;;;274    
;;;275        /* Disable TX start interrupt flag */
;;;276        if((u32Mask & USCI_SPI_TXSTIEN_MASK) == USCI_SPI_TXSTIEN_MASK)
000052  064c              LSLS     r4,r1,#25
000054  d502              BPL      |L6.92|
;;;277            usci->INTEN &= ~USCI_INTEN_TXSTIEN_Msk;
000056  6844              LDR      r4,[r0,#4]
000058  43ac              BICS     r4,r4,r5
00005a  6044              STR      r4,[r0,#4]
                  |L6.92|
;;;278    
;;;279        /* Disable TX end interrupt flag */
;;;280        if((u32Mask & USCI_SPI_TXENDIEN_MASK) == USCI_SPI_TXENDIEN_MASK)
00005c  060c              LSLS     r4,r1,#24
00005e  d502              BPL      |L6.102|
;;;281            usci->INTEN &= ~USCI_INTEN_TXENDIEN_Msk;
000060  6844              LDR      r4,[r0,#4]
000062  439c              BICS     r4,r4,r3
000064  6044              STR      r4,[r0,#4]
                  |L6.102|
;;;282    
;;;283        /* Disable RX start interrupt flag */
;;;284        if((u32Mask & USCI_SPI_RXSTIEN_MASK) == USCI_SPI_RXSTIEN_MASK)
000066  05cb              LSLS     r3,r1,#23
000068  d502              BPL      |L6.112|
;;;285            usci->INTEN &= ~USCI_INTEN_RXSTIEN_Msk;
00006a  6843              LDR      r3,[r0,#4]
00006c  4393              BICS     r3,r3,r2
00006e  6043              STR      r3,[r0,#4]
                  |L6.112|
;;;286    
;;;287        /* Disable RX end interrupt flag */
;;;288        if((u32Mask & USCI_SPI_RXENDIEN_MASK) == USCI_SPI_RXENDIEN_MASK)
000070  0589              LSLS     r1,r1,#22
000072  d503              BPL      |L6.124|
;;;289            usci->INTEN &= ~USCI_INTEN_RXENDIEN_Msk;
000074  6841              LDR      r1,[r0,#4]
000076  2210              MOVS     r2,#0x10
000078  4391              BICS     r1,r1,r2
00007a  6041              STR      r1,[r0,#4]
                  |L6.124|
;;;290    }
00007c  bd70              POP      {r4-r6,pc}
;;;291    
                          ENDP


                          AREA ||i.USCI_SPI_DisableWakeup||, CODE, READONLY, ALIGN=1

                  USCI_SPI_DisableWakeup PROC
;;;477      */
;;;478    void USCI_SPI_DisableWakeup(USCI_T *usci)
000000  6d41              LDR      r1,[r0,#0x54]
;;;479    {
;;;480        usci->WKCTL &= ~USCI_WKCTL_WKEN_Msk;
000002  0849              LSRS     r1,r1,#1
000004  0049              LSLS     r1,r1,#1
000006  6541              STR      r1,[r0,#0x54]
;;;481    }
000008  4770              BX       lr
;;;482    
                          ENDP


                          AREA ||i.USCI_SPI_EnableAutoSS||, CODE, READONLY, ALIGN=1

                  USCI_SPI_EnableAutoSS PROC
;;;129      */
;;;130    void USCI_SPI_EnableAutoSS(USCI_T *usci, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
000000  6a01              LDR      r1,[r0,#0x20]
;;;131    {
;;;132        usci->CTLIN0 = (usci->CTLIN0 & ~USCI_CTLIN0_ININV_Msk) | u32ActiveLevel;
000002  2304              MOVS     r3,#4
000004  4399              BICS     r1,r1,r3
000006  4311              ORRS     r1,r1,r2
000008  6201              STR      r1,[r0,#0x20]
;;;133        usci->PROTCTL |= USCI_PROTCTL_AUTOSS_Msk;
00000a  6dc1              LDR      r1,[r0,#0x5c]
00000c  2208              MOVS     r2,#8
00000e  4311              ORRS     r1,r1,r2
000010  65c1              STR      r1,[r0,#0x5c]
;;;134    }
000012  4770              BX       lr
;;;135    
                          ENDP


                          AREA ||i.USCI_SPI_EnableInt||, CODE, READONLY, ALIGN=1

                  USCI_SPI_EnableInt PROC
;;;187      */
;;;188    void USCI_SPI_EnableInt(USCI_T *usci, uint32_t u32Mask)
000000  b570              PUSH     {r4-r6,lr}
;;;189    {
;;;190        /* Enable slave selection signal inactive interrupt flag */
;;;191        if((u32Mask & USCI_SPI_SSINAIEN_MASK) == USCI_SPI_SSINAIEN_MASK)
000002  07ca              LSLS     r2,r1,#31
000004  d003              BEQ      |L9.14|
;;;192            usci->PROTIEN |= USCI_PROTIEN_SSINAIEN_Msk;
000006  6e02              LDR      r2,[r0,#0x60]
000008  2301              MOVS     r3,#1
00000a  431a              ORRS     r2,r2,r3
00000c  6602              STR      r2,[r0,#0x60]
                  |L9.14|
;;;193    
;;;194        /* Enable slave selection signal active interrupt flag */
;;;195        if((u32Mask & USCI_SPI_SSACTIEN_MASK) == USCI_SPI_SSACTIEN_MASK)
00000e  078a              LSLS     r2,r1,#30
;;;196            usci->PROTIEN |= USCI_PROTIEN_SSACTIEN_Msk;
000010  2402              MOVS     r4,#2
000012  2a00              CMP      r2,#0                 ;195
000014  da02              BGE      |L9.28|
000016  6e02              LDR      r2,[r0,#0x60]
000018  4322              ORRS     r2,r2,r4
00001a  6602              STR      r2,[r0,#0x60]
                  |L9.28|
;;;197    
;;;198        /* Enable slave time-out interrupt flag */
;;;199        if((u32Mask & USCI_SPI_SLVTOIEN_MASK) == USCI_SPI_SLVTOIEN_MASK)
00001c  074a              LSLS     r2,r1,#29
;;;200            usci->PROTIEN |= USCI_PROTIEN_SLVTOIEN_Msk;
00001e  2504              MOVS     r5,#4
000020  2a00              CMP      r2,#0                 ;199
000022  da02              BGE      |L9.42|
000024  6e02              LDR      r2,[r0,#0x60]
000026  432a              ORRS     r2,r2,r5
000028  6602              STR      r2,[r0,#0x60]
                  |L9.42|
;;;201    
;;;202        /* Enable slave bit count error interrupt flag */
;;;203        if((u32Mask & USCI_SPI_SLVBEIEN_MASK) == USCI_SPI_SLVBEIEN_MASK)
00002a  070a              LSLS     r2,r1,#28
;;;204            usci->PROTIEN |= USCI_PROTIEN_SLVBEIEN_Msk;
00002c  2308              MOVS     r3,#8
00002e  2a00              CMP      r2,#0                 ;203
000030  da02              BGE      |L9.56|
000032  6e02              LDR      r2,[r0,#0x60]
000034  431a              ORRS     r2,r2,r3
000036  6602              STR      r2,[r0,#0x60]
                  |L9.56|
;;;205    
;;;206        /* Enable TX under run interrupt flag */
;;;207        if((u32Mask & USCI_SPI_TXUDRIEN_MASK) == USCI_SPI_TXUDRIEN_MASK)
000038  06ca              LSLS     r2,r1,#27
00003a  d503              BPL      |L9.68|
;;;208            usci->BUFCTL |= USCI_BUFCTL_TXUDRIEN_Msk;
00003c  6b82              LDR      r2,[r0,#0x38]
00003e  2640              MOVS     r6,#0x40
000040  4332              ORRS     r2,r2,r6
000042  6382              STR      r2,[r0,#0x38]
                  |L9.68|
;;;209    
;;;210        /* Enable RX overrun interrupt flag */
;;;211        if((u32Mask & USCI_SPI_RXOVIEN_MASK) == USCI_SPI_RXOVIEN_MASK)
000044  068a              LSLS     r2,r1,#26
000046  d504              BPL      |L9.82|
;;;212            usci->BUFCTL |= USCI_BUFCTL_RXOVIEN_Msk;
000048  6b82              LDR      r2,[r0,#0x38]
00004a  2601              MOVS     r6,#1
00004c  03b6              LSLS     r6,r6,#14
00004e  4332              ORRS     r2,r2,r6
000050  6382              STR      r2,[r0,#0x38]
                  |L9.82|
;;;213    
;;;214        /* Enable TX start interrupt flag */
;;;215        if((u32Mask & USCI_SPI_TXSTIEN_MASK) == USCI_SPI_TXSTIEN_MASK)
000052  064a              LSLS     r2,r1,#25
000054  d502              BPL      |L9.92|
;;;216            usci->INTEN |= USCI_INTEN_TXSTIEN_Msk;
000056  6842              LDR      r2,[r0,#4]
000058  4322              ORRS     r2,r2,r4
00005a  6042              STR      r2,[r0,#4]
                  |L9.92|
;;;217    
;;;218        /* Enable TX end interrupt flag */
;;;219        if((u32Mask & USCI_SPI_TXENDIEN_MASK) == USCI_SPI_TXENDIEN_MASK)
00005c  060a              LSLS     r2,r1,#24
00005e  d502              BPL      |L9.102|
;;;220            usci->INTEN |= USCI_INTEN_TXENDIEN_Msk;
000060  6842              LDR      r2,[r0,#4]
000062  432a              ORRS     r2,r2,r5
000064  6042              STR      r2,[r0,#4]
                  |L9.102|
;;;221    
;;;222        /* Enable RX start interrupt flag */
;;;223        if((u32Mask & USCI_SPI_RXSTIEN_MASK) == USCI_SPI_RXSTIEN_MASK)
000066  05ca              LSLS     r2,r1,#23
000068  d502              BPL      |L9.112|
;;;224            usci->INTEN |= USCI_INTEN_RXSTIEN_Msk;
00006a  6842              LDR      r2,[r0,#4]
00006c  431a              ORRS     r2,r2,r3
00006e  6042              STR      r2,[r0,#4]
                  |L9.112|
;;;225    
;;;226        /* Enable RX end interrupt flag */
;;;227        if((u32Mask & USCI_SPI_RXENDIEN_MASK) == USCI_SPI_RXENDIEN_MASK)
000070  0589              LSLS     r1,r1,#22
000072  d503              BPL      |L9.124|
;;;228            usci->INTEN |= USCI_INTEN_RXENDIEN_Msk;
000074  6841              LDR      r1,[r0,#4]
000076  2210              MOVS     r2,#0x10
000078  4311              ORRS     r1,r1,r2
00007a  6041              STR      r1,[r0,#4]
                  |L9.124|
;;;229    }
00007c  bd70              POP      {r4-r6,pc}
;;;230    
                          ENDP


                          AREA ||i.USCI_SPI_EnableWakeup||, CODE, READONLY, ALIGN=1

                  USCI_SPI_EnableWakeup PROC
;;;467      */
;;;468    void USCI_SPI_EnableWakeup(USCI_T *usci)
000000  6d41              LDR      r1,[r0,#0x54]
;;;469    {
;;;470        usci->WKCTL |= USCI_WKCTL_WKEN_Msk;
000002  2201              MOVS     r2,#1
000004  4311              ORRS     r1,r1,r2
000006  6541              STR      r1,[r0,#0x54]
;;;471    }
000008  4770              BX       lr
;;;472    
                          ENDP


                          AREA ||i.USCI_SPI_GetBusClock||, CODE, READONLY, ALIGN=1

                  USCI_SPI_GetBusClock PROC
;;;160      */
;;;161    uint32_t USCI_SPI_GetBusClock(USCI_T *usci)
000000  b510              PUSH     {r4,lr}
;;;162    {
;;;163        uint32_t u32ClkDiv;
;;;164    
;;;165        u32ClkDiv = (usci->BRGEN & USCI_BRGEN_CLKDIV_Msk) >> USCI_BRGEN_CLKDIV_Pos;
000002  6880              LDR      r0,[r0,#8]
;;;166    
;;;167        return ( CLK_GetPCLKFreq() / ((u32ClkDiv+1)<<1) );
;;;168    }
000004  0180              LSLS     r0,r0,#6
000006  0d84              LSRS     r4,r0,#22
000008  f7fffffe          BL       CLK_GetPCLKFreq
00000c  0061              LSLS     r1,r4,#1              ;167
00000e  1c89              ADDS     r1,r1,#2              ;167
000010  f7fffffe          BL       __aeabi_uidivmod
000014  bd10              POP      {r4,pc}
;;;169    
                          ENDP


                          AREA ||i.USCI_SPI_GetIntFlag||, CODE, READONLY, ALIGN=1

                  USCI_SPI_GetIntFlag PROC
;;;309      */
;;;310    uint32_t USCI_SPI_GetIntFlag(USCI_T *usci, uint32_t u32Mask)
000000  4602              MOV      r2,r0
;;;311    {
;;;312        uint32_t u32IntFlag = 0;
000002  2000              MOVS     r0,#0
;;;313    
;;;314        /* Check slave selection signal inactive interrupt flag */
;;;315        if((u32Mask & USCI_SPI_SSINAIEN_MASK) && (usci->PROTSTS & USCI_PROTSTS_SSINAIF_Msk))
000004  07cb              LSLS     r3,r1,#31
000006  d003              BEQ      |L12.16|
000008  6e53              LDR      r3,[r2,#0x64]
00000a  05db              LSLS     r3,r3,#23
00000c  d500              BPL      |L12.16|
;;;316            u32IntFlag |= USCI_SPI_SSINAIEN_MASK;
00000e  2001              MOVS     r0,#1
                  |L12.16|
;;;317    
;;;318        /* Check slave selection signal active interrupt flag */
;;;319        if((u32Mask & USCI_SPI_SSACTIEN_MASK) && (usci->PROTSTS & USCI_PROTSTS_SSACTIF_Msk))
000010  078b              LSLS     r3,r1,#30
000012  d504              BPL      |L12.30|
000014  6e53              LDR      r3,[r2,#0x64]
000016  059b              LSLS     r3,r3,#22
000018  d501              BPL      |L12.30|
;;;320            u32IntFlag |= USCI_SPI_SSACTIEN_MASK;
00001a  2302              MOVS     r3,#2
00001c  4318              ORRS     r0,r0,r3
                  |L12.30|
;;;321    
;;;322        /* Check slave time-out interrupt flag */
;;;323        if((u32Mask & USCI_SPI_SLVTOIEN_MASK) && (usci->PROTSTS & USCI_PROTSTS_SLVTOIF_Msk))
00001e  074b              LSLS     r3,r1,#29
000020  d504              BPL      |L12.44|
000022  6e53              LDR      r3,[r2,#0x64]
000024  069b              LSLS     r3,r3,#26
000026  d501              BPL      |L12.44|
;;;324            u32IntFlag |= USCI_SPI_SLVTOIEN_MASK;
000028  2304              MOVS     r3,#4
00002a  4318              ORRS     r0,r0,r3
                  |L12.44|
;;;325    
;;;326        /* Check slave bit count error interrupt flag */
;;;327        if((u32Mask & USCI_SPI_SLVBEIEN_MASK) && (usci->PROTSTS & USCI_PROTSTS_SLVBEIF_Msk))
00002c  070b              LSLS     r3,r1,#28
00002e  d504              BPL      |L12.58|
000030  6e53              LDR      r3,[r2,#0x64]
000032  065b              LSLS     r3,r3,#25
000034  d501              BPL      |L12.58|
;;;328            u32IntFlag |= USCI_SPI_SLVBEIEN_MASK;
000036  2308              MOVS     r3,#8
000038  4318              ORRS     r0,r0,r3
                  |L12.58|
;;;329    
;;;330        /* Check TX under run interrupt flag */
;;;331        if((u32Mask & USCI_SPI_TXUDRIEN_MASK) && (usci->BUFSTS & USCI_BUFSTS_TXUDRIF_Msk))
00003a  06cb              LSLS     r3,r1,#27
00003c  d504              BPL      |L12.72|
00003e  6bd3              LDR      r3,[r2,#0x3c]
000040  051b              LSLS     r3,r3,#20
000042  d501              BPL      |L12.72|
;;;332            u32IntFlag |= USCI_SPI_TXUDRIEN_MASK;
000044  2310              MOVS     r3,#0x10
000046  4318              ORRS     r0,r0,r3
                  |L12.72|
;;;333    
;;;334        /* Check RX overrun interrupt flag */
;;;335        if((u32Mask & USCI_SPI_RXOVIEN_MASK) && (usci->BUFSTS & USCI_BUFSTS_RXOVIF_Msk))
000048  068b              LSLS     r3,r1,#26
00004a  d504              BPL      |L12.86|
00004c  6bd3              LDR      r3,[r2,#0x3c]
00004e  071b              LSLS     r3,r3,#28
000050  d501              BPL      |L12.86|
;;;336            u32IntFlag |= USCI_SPI_RXOVIEN_MASK;
000052  2320              MOVS     r3,#0x20
000054  4318              ORRS     r0,r0,r3
                  |L12.86|
;;;337    
;;;338        /* Check TX start interrupt flag */
;;;339        if((u32Mask & USCI_SPI_TXSTIEN_MASK) && (usci->PROTSTS & USCI_PROTSTS_TXSTIF_Msk))
000056  064b              LSLS     r3,r1,#25
000058  d504              BPL      |L12.100|
00005a  6e53              LDR      r3,[r2,#0x64]
00005c  079b              LSLS     r3,r3,#30
00005e  d501              BPL      |L12.100|
;;;340            u32IntFlag |= USCI_SPI_TXSTIEN_MASK;
000060  2340              MOVS     r3,#0x40
000062  4318              ORRS     r0,r0,r3
                  |L12.100|
;;;341    
;;;342        /* Check TX end interrupt flag */
;;;343        if((u32Mask & USCI_SPI_TXENDIEN_MASK) && (usci->PROTSTS & USCI_PROTSTS_TXENDIF_Msk))
000064  060b              LSLS     r3,r1,#24
000066  d504              BPL      |L12.114|
000068  6e53              LDR      r3,[r2,#0x64]
00006a  075b              LSLS     r3,r3,#29
00006c  d501              BPL      |L12.114|
;;;344            u32IntFlag |= USCI_SPI_TXENDIEN_MASK;
00006e  2380              MOVS     r3,#0x80
000070  4318              ORRS     r0,r0,r3
                  |L12.114|
;;;345    
;;;346        /* Check RX start interrupt flag */
;;;347        if((u32Mask & USCI_SPI_RXSTIEN_MASK) && (usci->PROTSTS & USCI_PROTSTS_RXSTIF_Msk))
000072  05cb              LSLS     r3,r1,#23
000074  d505              BPL      |L12.130|
000076  6e53              LDR      r3,[r2,#0x64]
000078  071b              LSLS     r3,r3,#28
00007a  d502              BPL      |L12.130|
;;;348            u32IntFlag |= USCI_SPI_RXSTIEN_MASK;
00007c  23ff              MOVS     r3,#0xff
00007e  3301              ADDS     r3,#1
000080  4318              ORRS     r0,r0,r3
                  |L12.130|
;;;349    
;;;350        /* Check RX end interrupt flag */
;;;351        if((u32Mask & USCI_SPI_RXENDIEN_MASK) && (usci->PROTSTS & USCI_PROTSTS_RXENDIF_Msk))
000082  0589              LSLS     r1,r1,#22
000084  d505              BPL      |L12.146|
000086  6e51              LDR      r1,[r2,#0x64]
000088  06c9              LSLS     r1,r1,#27
00008a  d502              BPL      |L12.146|
;;;352            u32IntFlag |= USCI_SPI_RXENDIEN_MASK;
00008c  2101              MOVS     r1,#1
00008e  0249              LSLS     r1,r1,#9
000090  4308              ORRS     r0,r0,r1
                  |L12.146|
;;;353    
;;;354        return u32IntFlag;
;;;355    }
000092  4770              BX       lr
;;;356    
                          ENDP


                          AREA ||i.USCI_SPI_GetStatus||, CODE, READONLY, ALIGN=1

                  USCI_SPI_GetStatus PROC
;;;431      */
;;;432    uint32_t USCI_SPI_GetStatus(USCI_T *usci, uint32_t u32Mask)
000000  4602              MOV      r2,r0
;;;433    {
;;;434        uint32_t u32Flag = 0;
000002  2000              MOVS     r0,#0
;;;435    
;;;436        /* Check busy status */
;;;437        if((u32Mask & SPI_BUSY_MASK) && (usci->PROTSTS & USCI_PROTSTS_BUSY_Msk))
000004  07cb              LSLS     r3,r1,#31
000006  d003              BEQ      |L13.16|
000008  6e53              LDR      r3,[r2,#0x64]
00000a  039b              LSLS     r3,r3,#14
00000c  d500              BPL      |L13.16|
;;;438            u32Flag |= SPI_BUSY_MASK;
00000e  2001              MOVS     r0,#1
                  |L13.16|
;;;439    
;;;440        /* Check RX empty flag */
;;;441        if((u32Mask & SPI_RX_EMPTY_MASK) && (usci->BUFSTS & USCI_BUFSTS_RXEMPTY_Msk))
000010  078b              LSLS     r3,r1,#30
000012  d504              BPL      |L13.30|
000014  6bd3              LDR      r3,[r2,#0x3c]
000016  07db              LSLS     r3,r3,#31
000018  d001              BEQ      |L13.30|
;;;442            u32Flag |= SPI_RX_EMPTY_MASK;
00001a  2302              MOVS     r3,#2
00001c  4318              ORRS     r0,r0,r3
                  |L13.30|
;;;443    
;;;444        /* Check RX full flag */
;;;445        if((u32Mask & SPI_RX_FULL_MASK) && (usci->BUFSTS & USCI_BUFSTS_RXFULL_Msk))
00001e  074b              LSLS     r3,r1,#29
000020  d504              BPL      |L13.44|
000022  6bd3              LDR      r3,[r2,#0x3c]
000024  079b              LSLS     r3,r3,#30
000026  d501              BPL      |L13.44|
;;;446            u32Flag |= SPI_RX_FULL_MASK;
000028  2304              MOVS     r3,#4
00002a  4318              ORRS     r0,r0,r3
                  |L13.44|
;;;447    
;;;448        /* Check TX empty flag */
;;;449        if((u32Mask & SPI_TX_EMPTY_MASK) && (usci->BUFSTS & USCI_BUFSTS_TXEMPTY_Msk))
00002c  070b              LSLS     r3,r1,#28
00002e  d504              BPL      |L13.58|
000030  6bd3              LDR      r3,[r2,#0x3c]
000032  05db              LSLS     r3,r3,#23
000034  d501              BPL      |L13.58|
;;;450            u32Flag |= SPI_TX_EMPTY_MASK;
000036  2308              MOVS     r3,#8
000038  4318              ORRS     r0,r0,r3
                  |L13.58|
;;;451    
;;;452        /* Check TX full flag */
;;;453        if((u32Mask & SPI_TX_FULL_MASK) && (usci->BUFSTS & USCI_BUFSTS_TXFULL_Msk))
00003a  06cb              LSLS     r3,r1,#27
00003c  d504              BPL      |L13.72|
00003e  6bd3              LDR      r3,[r2,#0x3c]
000040  059b              LSLS     r3,r3,#22
000042  d501              BPL      |L13.72|
;;;454            u32Flag |= SPI_TX_FULL_MASK;
000044  2310              MOVS     r3,#0x10
000046  4318              ORRS     r0,r0,r3
                  |L13.72|
;;;455    
;;;456        /* Check USCI_SPI_SS line status */
;;;457        if((u32Mask & SPI_SSLINE_STS_MASK) && (usci->PROTSTS & USCI_PROTSTS_SSLINE_Msk))
000048  0689              LSLS     r1,r1,#26
00004a  d504              BPL      |L13.86|
00004c  6e51              LDR      r1,[r2,#0x64]
00004e  03c9              LSLS     r1,r1,#15
000050  d501              BPL      |L13.86|
;;;458            u32Flag |= SPI_SSLINE_STS_MASK;
000052  2120              MOVS     r1,#0x20
000054  4308              ORRS     r0,r0,r1
                  |L13.86|
;;;459    
;;;460        return u32Flag;
;;;461    }
000056  4770              BX       lr
;;;462    
                          ENDP


                          AREA ||i.USCI_SPI_Open||, CODE, READONLY, ALIGN=2

                  USCI_SPI_Open PROC
;;;44       */
;;;45     uint32_t USCI_SPI_Open(USCI_T *usci, uint32_t u32MasterSlave, uint32_t u32SPIMode,  uint32_t u32DataWidth, uint32_t u32BusClock)
000000  b5ff              PUSH     {r0-r7,lr}
;;;46     {
000002  b081              SUB      sp,sp,#4
000004  461e              MOV      r6,r3
000006  4604              MOV      r4,r0
;;;47         uint32_t u32ClkDiv = 0;
000008  2500              MOVS     r5,#0
;;;48         uint32_t u32Pclk = CLK_GetPCLKFreq();
00000a  f7fffffe          BL       CLK_GetPCLKFreq
00000e  4607              MOV      r7,r0
;;;49     
;;;50         if(u32BusClock != 0)
000010  980a              LDR      r0,[sp,#0x28]
000012  2800              CMP      r0,#0
000014  d00a              BEQ      |L14.44|
;;;51             u32ClkDiv = (uint32_t) ((((((u32Pclk/2)*10)/(u32BusClock))+5)/10)-1); /* Compute proper divider for USCI_SPI clock */
000016  0878              LSRS     r0,r7,#1
000018  210a              MOVS     r1,#0xa
00001a  4348              MULS     r0,r1,r0
00001c  990a              LDR      r1,[sp,#0x28]
00001e  f7fffffe          BL       __aeabi_uidivmod
000022  210a              MOVS     r1,#0xa
000024  1d40              ADDS     r0,r0,#5
000026  f7fffffe          BL       __aeabi_uidivmod
00002a  1e45              SUBS     r5,r0,#1
                  |L14.44|
;;;52     
;;;53         /* Enable USCI_SPI protocol */
;;;54         usci->CTL &= ~USCI_CTL_FUNMODE_Msk;
00002c  6820              LDR      r0,[r4,#0]
00002e  08c0              LSRS     r0,r0,#3
000030  00c0              LSLS     r0,r0,#3
000032  6020              STR      r0,[r4,#0]
;;;55         usci->CTL = 1 << USCI_CTL_FUNMODE_Pos;
000034  2001              MOVS     r0,#1
000036  6020              STR      r0,[r4,#0]
;;;56     
;;;57         /* Data format configuration */
;;;58         if(u32DataWidth == 16)
000038  2e10              CMP      r6,#0x10
00003a  d100              BNE      |L14.62|
;;;59             u32DataWidth = 0;
00003c  2600              MOVS     r6,#0
                  |L14.62|
;;;60         usci->LINECTL &= ~USCI_LINECTL_DWIDTH_Msk;
00003e  6ae0              LDR      r0,[r4,#0x2c]
000040  210f              MOVS     r1,#0xf
000042  0209              LSLS     r1,r1,#8
000044  4388              BICS     r0,r0,r1
000046  62e0              STR      r0,[r4,#0x2c]
;;;61         usci->LINECTL |= (u32DataWidth << USCI_LINECTL_DWIDTH_Pos);
000048  6ae0              LDR      r0,[r4,#0x2c]
00004a  0231              LSLS     r1,r6,#8
00004c  4308              ORRS     r0,r0,r1
00004e  62e0              STR      r0,[r4,#0x2c]
;;;62     
;;;63         /* MSB data format */
;;;64         usci->LINECTL &= ~USCI_LINECTL_LSB_Msk;
000050  6ae0              LDR      r0,[r4,#0x2c]
000052  0840              LSRS     r0,r0,#1
000054  0040              LSLS     r0,r0,#1
000056  62e0              STR      r0,[r4,#0x2c]
;;;65     
;;;66         /* Set operating mode and transfer timing */
;;;67         usci->PROTCTL &= ~(USCI_PROTCTL_SCLKMODE_Msk | USCI_PROTCTL_AUTOSS_Msk | USCI_PROTCTL_SLAVE_Msk);
000058  6de0              LDR      r0,[r4,#0x5c]
00005a  21c9              MOVS     r1,#0xc9
00005c  4388              BICS     r0,r0,r1
00005e  65e0              STR      r0,[r4,#0x5c]
;;;68         usci->PROTCTL |= (u32MasterSlave | u32SPIMode);
000060  6de1              LDR      r1,[r4,#0x5c]
000062  9a03              LDR      r2,[sp,#0xc]
000064  9802              LDR      r0,[sp,#8]
000066  4310              ORRS     r0,r0,r2
000068  4301              ORRS     r1,r1,r0
00006a  65e1              STR      r1,[r4,#0x5c]
;;;69     
;;;70         /* Set USCI_SPI bus clock */
;;;71         usci->BRGEN &= ~USCI_BRGEN_CLKDIV_Msk;
00006c  68a0              LDR      r0,[r4,#8]
00006e  490b              LDR      r1,|L14.156|
000070  4008              ANDS     r0,r0,r1
000072  60a0              STR      r0,[r4,#8]
;;;72         usci->BRGEN |=  (u32ClkDiv << USCI_BRGEN_CLKDIV_Pos);
000074  68a0              LDR      r0,[r4,#8]
000076  0429              LSLS     r1,r5,#16
000078  4308              ORRS     r0,r0,r1
00007a  60a0              STR      r0,[r4,#8]
;;;73         usci->PROTCTL |=  USCI_PROTCTL_PROTEN_Msk;
00007c  6de0              LDR      r0,[r4,#0x5c]
00007e  2101              MOVS     r1,#1
000080  07c9              LSLS     r1,r1,#31
000082  4308              ORRS     r0,r0,r1
000084  65e0              STR      r0,[r4,#0x5c]
;;;74     
;;;75         if(u32BusClock != 0)
000086  980a              LDR      r0,[sp,#0x28]
000088  2800              CMP      r0,#0
00008a  d004              BEQ      |L14.150|
;;;76             return ( u32Pclk / ((u32ClkDiv+1)<<1) );
00008c  0069              LSLS     r1,r5,#1
00008e  4638              MOV      r0,r7
000090  1c89              ADDS     r1,r1,#2
000092  f7fffffe          BL       __aeabi_uidivmod
                  |L14.150|
;;;77         else
;;;78             return 0;
;;;79     }
000096  b005              ADD      sp,sp,#0x14
000098  bdf0              POP      {r4-r7,pc}
;;;80     
                          ENDP

00009a  0000              DCW      0x0000
                  |L14.156|
                          DCD      0xfc00ffff

                          AREA ||i.USCI_SPI_SetBusClock||, CODE, READONLY, ALIGN=2

                  USCI_SPI_SetBusClock PROC
;;;141      */
;;;142    uint32_t USCI_SPI_SetBusClock(USCI_T *usci, uint32_t u32BusClock)
000000  b570              PUSH     {r4-r6,lr}
;;;143    {
000002  460e              MOV      r6,r1
000004  4604              MOV      r4,r0
;;;144        uint32_t u32ClkDiv;
;;;145        uint32_t u32Pclk = CLK_GetPCLKFreq();
000006  f7fffffe          BL       CLK_GetPCLKFreq
00000a  4605              MOV      r5,r0
;;;146    
;;;147        u32ClkDiv = (uint32_t) ((((((u32Pclk/2)*10)/(u32BusClock))+5)/10)-1); /* Compute proper divider for USCI_SPI clock */
00000c  0840              LSRS     r0,r0,#1
00000e  210a              MOVS     r1,#0xa
000010  4348              MULS     r0,r1,r0
000012  4631              MOV      r1,r6
000014  f7fffffe          BL       __aeabi_uidivmod
000018  210a              MOVS     r1,#0xa
00001a  1d40              ADDS     r0,r0,#5
00001c  f7fffffe          BL       __aeabi_uidivmod
;;;148    
;;;149        /* Set USCI_SPI bus clock */
;;;150        usci->BRGEN &= ~USCI_BRGEN_CLKDIV_Msk;
000020  68a1              LDR      r1,[r4,#8]
000022  4a07              LDR      r2,|L15.64|
000024  4011              ANDS     r1,r1,r2
000026  60a1              STR      r1,[r4,#8]
;;;151        usci->BRGEN |=  (u32ClkDiv << USCI_BRGEN_CLKDIV_Pos);
000028  68a1              LDR      r1,[r4,#8]
00002a  1e40              SUBS     r0,r0,#1
00002c  0402              LSLS     r2,r0,#16
00002e  4311              ORRS     r1,r1,r2
000030  60a1              STR      r1,[r4,#8]
;;;152    
;;;153        return ( u32Pclk / ((u32ClkDiv+1)<<1) );
000032  0041              LSLS     r1,r0,#1
000034  4628              MOV      r0,r5
000036  1c89              ADDS     r1,r1,#2
000038  f7fffffe          BL       __aeabi_uidivmod
;;;154    }
00003c  bd70              POP      {r4-r6,pc}
;;;155    
                          ENDP

00003e  0000              DCW      0x0000
                  |L15.64|
                          DCD      0xfc00ffff

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\usci_spi.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___10_usci_spi_c_9fb47a95____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___10_usci_spi_c_9fb47a95____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___10_usci_spi_c_9fb47a95____REVSH|
#line 132
|__asm___10_usci_spi_c_9fb47a95____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
