; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\system_nm1240.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\system_nm1240.d --cpu=Cortex-M0 --apcs=interwork --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\NM1240\Include -I..\..\..\Library\StdDriver\inc -I.\RTE\_Template -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.4.0\CMSIS\Core\Include -IC:\Keil_v5\ARM\PACK\Nuvoton\NuMicro_DFP\1.3.9\Device\NM1230\Include -D__MICROLIB -D__UVISION_VERSION=526 -D_RTE_ --omf_browse=.\obj\system_nm1240.crf ..\..\..\Library\Device\Nuvoton\NM1240\Source\system_NM1240.c]
                          THUMB

                          AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;29      *----------------------------------------------------------------------------*/
;;;30     void SystemCoreClockUpdate(void)
000000  b510              PUSH     {r4,lr}
;;;31     {
;;;32         uint32_t u32Freq, u32ClkSrc;
;;;33         uint32_t u32HclkDiv;
;;;34     
;;;35         __HIRC = (CLK->PWRCTL & CLK_PWRCTL_HIRC_SEL_Msk) ? FREQ_60MHZ : FREQ_48MHZ;
000002  4a12              LDR      r2,|L1.76|
000004  6810              LDR      r0,[r2,#0]
000006  01c0              LSLS     r0,r0,#7
000008  d501              BPL      |L1.14|
00000a  4811              LDR      r0,|L1.80|
00000c  e000              B        |L1.16|
                  |L1.14|
00000e  4811              LDR      r0,|L1.84|
                  |L1.16|
000010  4c11              LDR      r4,|L1.88|
;;;36         u32ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk) >> CLK_CLKSEL0_HCLKSEL_Pos;
000012  6020              STR      r0,[r4,#0]  ; __HIRC
000014  6911              LDR      r1,[r2,#0x10]
000016  0789              LSLS     r1,r1,#30
000018  0f89              LSRS     r1,r1,#30
;;;37         if (u32ClkSrc == 0)
00001a  d012              BEQ      |L1.66|
;;;38         {
;;;39             u32Freq = __EXT;
;;;40         }
;;;41         else if (u32ClkSrc == 1)
00001c  2901              CMP      r1,#1
00001e  d012              BEQ      |L1.70|
;;;42         {
;;;43             u32Freq = __LIRC;
;;;44         }
;;;45         else if (u32ClkSrc == 3)
000020  2903              CMP      r1,#3
000022  d000              BEQ      |L1.38|
;;;46         {
;;;47             u32Freq = __HIRC;
;;;48         }
;;;49         else
;;;50         {
;;;51             u32Freq = NULL;
000024  2000              MOVS     r0,#0
                  |L1.38|
;;;52         }
;;;53         u32HclkDiv = ((CLK->CLKDIV & CLK_CLKDIV_HCLKDIV_Msk) >> CLK_CLKDIV_HCLKDIV_Pos) + 1;
000026  6a11              LDR      r1,[r2,#0x20]
000028  0709              LSLS     r1,r1,#28
00002a  0f09              LSRS     r1,r1,#28
00002c  1c49              ADDS     r1,r1,#1
;;;54     
;;;55         /* Update System Core Clock */
;;;56         SystemCoreClock = u32Freq / u32HclkDiv;
00002e  f7fffffe          BL       __aeabi_uidivmod
;;;57     
;;;58         CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
000032  490a              LDR      r1,|L1.92|
000034  6060              STR      r0,[r4,#4]  ; SystemCoreClock
000036  104a              ASRS     r2,r1,#1
000038  1880              ADDS     r0,r0,r2
00003a  f7fffffe          BL       __aeabi_uidivmod
00003e  60a0              STR      r0,[r4,#8]  ; CyclesPerUs
;;;59     #if DEBUG
;;;60         printf("SystemCoreClockUpdate(): u32ClkSrc=%d, u32Freq=%d, u32HclkDiv=%d, SystemCoreClock=%d\n",
;;;61             u32ClkSrc, u32Freq, u32HclkDiv, SystemCoreClock);
;;;62     #endif
;;;63     }
000040  bd10              POP      {r4,pc}
                  |L1.66|
000042  4807              LDR      r0,|L1.96|
000044  e7ef              B        |L1.38|
                  |L1.70|
000046  4807              LDR      r0,|L1.100|
000048  e7ed              B        |L1.38|
;;;64     
                          ENDP

00004a  0000              DCW      0x0000
                  |L1.76|
                          DCD      0x50000200
                  |L1.80|
                          DCD      0x03938700
                  |L1.84|
                          DCD      0x02dc6c00
                  |L1.88|
                          DCD      ||.data||
                  |L1.92|
                          DCD      0x000f4240
                  |L1.96|
                          DCD      0x016e3600
                  |L1.100|
                          DCD      0x00002710

                          AREA ||i.SystemInit||, CODE, READONLY, ALIGN=1

                  SystemInit PROC
;;;77     /*---------------------------------------------------------------------------------------------------------*/
;;;78     void SystemInit(void)
000000  4770              BX       lr
;;;79     {
;;;80     }
;;;81     /*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
                          ENDP


                          AREA ||.data||, DATA, ALIGN=2

                  __HIRC
                          DCD      0x02dc6c00
                  SystemCoreClock
                          DCD      0x02dc6c00
                  CyclesPerUs
                          DCD      0x00000030

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Library\\Device\\Nuvoton\\NM1240\\Source\\system_NM1240.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___15_system_NM1240_c___HIRC____REV16|
#line 388 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|__asm___15_system_NM1240_c___HIRC____REV16| PROC
#line 389

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___15_system_NM1240_c___HIRC____REVSH|
#line 402
|__asm___15_system_NM1240_c___HIRC____REVSH| PROC
#line 403

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
