SPI FIFO TX interrupt mask

assman · 发表于 2021-9-27 16:18:02

各位大大安安，我想请问在官方SPI FIFO Mode范例里，Tx 和 Rx都使用FIFO传输，其中enable "SPI_FIFO_TX_INT_MASK"这项中断功能主要是什么意思
在IRQHandler动作是什么，谢谢!

/* Set TX FIFO threshold, enable TX FIFO threshold interrupt and RX FIFO time-out interrupt */
SPI_EnableFIFO(SPI0, 4, 4);
SPI_EnableInt(SPI0, SPI_FIFO_TX_INT_MASK | SPI_FIFO_TIMEOUT_INT_MASK);

void SPI0_IRQHandler(void)
{
/* Check RX EMPTY flag */
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0) == 0)
{
      /* Read RX FIFO */
      g_au32DestinationData[g_u32RxDataCount++] = SPI_READ_RX0(SPI0);
}
/* Check TX FULL flag and TX data count */
while((SPI_GET_TX_FIFO_FULL_FLAG(SPI0) == 0) && (g_u32TxDataCount < TEST_COUNT))
{
      /* Write to TX FIFO */
      SPI_WRITE_TX0(SPI0, g_au32SourceData[g_u32TxDataCount++]);
}
if(g_u32TxDataCount >= TEST_COUNT)
      SPI_DisableInt(SPI0, SPI_FIFO_TX_INT_MASK); /* Disable TX FIFO threshold interrupt */

/* Check the RX FIFO time-out interrupt flag */
if(SPI_GetIntFlag(SPI0, SPI_FIFO_TIMEOUT_INT_MASK))
{
      /* If RX FIFO is not empty, read RX FIFO. */
      while((SPI0->STATUS & SPI_STATUS_RX_EMPTY_Msk) == 0)
         g_au32DestinationData[g_u32RxDataCount++] = SPI_READ_RX0(SPI0);
}
}

assman · 发表于 2021-10-4 14:45:28

找到答案了，SPI_FIFO_TX_INT_MASK就是发送FIFO中断~

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[NUC] SPI FIFO TX interrupt mask