关于NUC123 数据参考手册USB 部分疑问

在USB部分 关于端点0~5 在整个寻址空间内部有两个地方，一个是0x020，另一个是0x500，不知道这样的用意是啥？但是库用的是0x500部分地址。
比如：USB_MXPLD0~5
USB_CFGP0~5
6.16.6Page 486 of 532

1. typedef struct
   
2. {
   
3. 
   
4. 
   
5. /**
   
6. * @var USBD_EP_T::BUFSEG0
   
7. * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570  Endpoint 0~7 Buffer Segmentation Register
   
8. * ---------------------------------------------------------------------------------------------------
   
9. * |Bits    |Field     |Descriptions
   
10. * | :----: | :----:   | :---- |
    
11. * |[8:3]   |BUFSEG    |Endpoint Buffer Segmentation
    
12. * |        |          |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
    
13. * |        |          |USB_SRAM address + { BUFSEG[8:3], 3'b000}
    
14. * |        |          |Where the USB_SRAM address = USBD_BA+0x100h.
    
15. * @var USBD_EP_T::MXPLD0
    
16. * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574  Endpoint 0~7 Maximal Payload Register
    
17. * ---------------------------------------------------------------------------------------------------
    
18. * |Bits    |Field     |Descriptions
    
19. * | :----: | :----:   | :---- |
    
20. * |[8:0]   |MXPLD     |Maximal Payload
    
21. * |        |          |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token).
    
22. * |        |          |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
    
23. * |        |          |(1) When the register is written by CPU,
    
24. * |        |          |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
    
25. * |        |          |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
    
26. * |        |          |(2) When the register is read by CPU,
    
27. * |        |          |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
    
28. * |        |          |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
    
29. * |        |          |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
    
30. * @var USBD_EP_T::CFG0
    
31. * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578  Endpoint 0~7 Configuration Register
    
32. * ---------------------------------------------------------------------------------------------------
    
33. * |Bits    |Field     |Descriptions
    
34. * | :----: | :----:   | :---- |
    
35. * |[3:0]   |EP_NUM    |Endpoint Number
    
36. * |        |          |These bits are used to define the endpoint number of the current endpoint.
    
37. * |[4]     |ISOCH     |Isochronous Endpoint
    
38. * |        |          |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
    
39. * |        |          |0 = No Isochronous endpoint.
    
40. * |        |          |1 = Isochronous endpoint.
    
41. * |[6:5]   |STATE     |Endpoint STATE
    
42. * |        |          |00 = Endpoint is Disabled.
    
43. * |        |          |01 = Out endpoint.
    
44. * |        |          |10 = IN endpoint.
    
45. * |        |          |11 = Undefined.
    
46. * |[7]     |DSQ_SYNC  |Data Sequence Synchronization
    
47. * |        |          |0 = DATA0 PID.
    
48. * |        |          |1 = DATA1 PID.
    
49. * |        |          |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction.
    
50. * |        |          |Hardware will toggle automatically in IN token base on the bit.
    
51. * |[9]     |CSTALL    |Clear STALL Response
    
52. * |        |          |0 = Disable the device to clear the STALL handshake in setup stage.
    
53. * |        |          |1 = Clear the device to response STALL handshake in setup stage.
    
54. * @var USBD_EP_T::CFGP0
    
55. * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C  Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register
    
56.     * ---------------------------------------------------------------------------------------------------
    
57.     * |Bits    |Field     |Descriptions
    
58.     * | :----: | :----:   | :---- |
    
59.     * |[0]     |CLRRDY    |Clear Ready
    
60.     * |        |          |When the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data.
    
61.     * |        |          |If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it will be cleared to 0 automatically.
    
62.     * |        |          |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
    
63.     * |        |          |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
    
64.     * |        |          |This bit is write 1 only and is always 0 when it is read back.
    
65.     * |[1]     |SSTALL    |Set STALL
    
66.     * |        |          |0 = Disable the device to response STALL.
    
67.     * |        |          |1 = Set the device to respond STALL automatically.
    
68.     */
    
69. 
    
70.     __IO uint32_t BUFSEG;        /* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570  Endpoint 0~7 Buffer Segmentation Register */
    
71.     __IO uint32_t MXPLD;         /* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574  Endpoint 0~7 Maximal Payload Register */
    
72.     __IO uint32_t CFG;           /* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578  Endpoint 0~7 Configuration Register */
    
73.     __IO uint32_t CFGP;          /* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C  Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register */
    
74. 
    
75. } USBD_EP_T;
    

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