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- CLK->PWRCTL |= CLK_PWRCTL_HIRC_F_STOP_Msk |CLK_PWRCTL_HIRC_FSEL_Msk;
-
- /* Enable external 16MHz HIRC, 32KHz LXT and LIRC */
- CLK_EnableXtalRC( CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk | CLK_CLKSTATUS_LIRC_STB_Msk);
-
- CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk|CLK_CLKSTATUS_LXT_STB_Msk|CLK_CLKSTATUS_LIRC_STB_Msk);
-
- /* Set HCLK frequency 32MHz */
- CLK->PLLCTL |= CLK_PLLCTL_PLL_SRC_HIRC;
- u32PLLReg = (32<<CLK_PLLCTL_PLL_MLP_Pos) | (15<<CLK_PLLCTL_PLL_SRC_N_Pos);
- CLK->PLLCTL = ( CLK->PLLCTL & ~(CLK_PLLCTL_PLL_MLP_Msk | CLK_PLLCTL_PLL_SRC_N_Msk ) )| u32PLLReg;
- CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
- CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
- CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_HCLK_CLK_DIVIDER(1));
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